An Indexed Bibliography of Genetic Algorithms in Electronics and VLSI Design and Testing

An Indexed Bibliography of Genetic Algorithms in Electronics and VLSI Design and Testing compiled by

Jarmo T. Alander

Department of Information Technology and Production Economics University of Vaasa P.O. Box 700, FIN-65101 Vaasa, Finland e-mail: [email protected] www: http://www.uwasa.fi/~ jal phone: +358-6-324 8444 fax: +358-6-324 8467 Report Series No. 94-1-VLSI

DRAFT January 6, 1999 available via anonymous ftp: site ftp.uwasa.fi directory cs/report94-1 le gaVLSIbib.ps.Z

c 1994, 1995, 1996, 1997, 1998 Jarmo T. Alander Copyright

Trademarks Product and company names listed are trademarks or trade names of their respective companies.

Warning While this bibliography has been compiled with the utmost care, the editor takes no responsibility for any errors, missing information, the contents or quality of the references, nor for the usefulness and/or the consequences of their application. The fact that a reference is included in this publication does not imply a recommendation. The use of any of the methods in the references is entirely at the user's own responsibility. Especially the above warning applies to those references that are marked by trailing 'y' (or '*'), which are the ones that the editor has unfortunately not had the opportunity to read. An abstract was available of the references marked with '*'.

Contents 1 Preface

1.1 Your contributions erroneous or missing? 1.1.1 How to cite this report? . . . . . . 1.2 How to get this report via Internet? . . 1.3 Acknowledgement . . . . . . . . . . . . . .

2 Introduction 3 Statistical summaries 3.1 3.2 3.3 3.4 3.5 3.6

Publication type . . . . . Annual distribution . . . . Classi cation . . . . . . . Authors . . . . . . . . . . Geographical distribution Conclusions and future . .

4 Indexes

4.1 Books . . . . . . . . . 4.2 Journal articles . . . . 4.3 Theses . . . . . . . . . 4.3.1 PhD theses . . 4.3.2 Master's theses 4.4 Report series . . . . . 4.5 Patents . . . . . . . . 4.6 Authors . . . . . . . . 4.7 Subject index . . . . . 4.8 Annual index . . . . . 4.9 Geographical index . .

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5 Permuted title index Bibliography Appendixes A Abbreviations B Bibliography entry formats

11

11 11 12 12 12 12 12 13 17 20 21

23 39 59 59 60

i

List of Tables 1.1 Indexed GA subbibliographies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3

2.1 Queries used to extract this subbibliography from the main database. . . . . . . . . . . .

5

3.1 3.2 3.3 3.4 3.5

7 7 8 8 9

Distribution of publication type. . . . . . . . . . . . . . . . Annual distribution of contributions. . . . . . . . . . . . . The most popular subjects. . . . . . . . . . . . . . . . . . . The most productive genetic algorithms and VLSI authors. The geographical distribution of the authors. . . . . . . . .

ii

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Chapter 1

Preface \Living organism are consummate problem solvers. They exhibit a versatility that puts the best computer programs to shame." [1] John H. Holland

The material of this bibliography has been extracted from the genetic algorithm bibliography [2], which when this report was compiled contained 11108 items and which has been collected from several sources of genetic algorithm literature including Usenet newsgroup comp.ai.genetic and the bibliographies [3, 4, 5, 6]. The following index periodicals have been used systematically  A: International Aerospace Abstracts: Jan. 1995 { Mar. 1998  ACM: ACM Guide to Computing Literature: 1979 { 1993/4  BA: Biological Abstracts: July 1996 - Aug. 1998  CA: Computer Abstracts: Jan. 1993 { Feb. 1995  CCA: Computer & Control Abstracts: Jan. 1992 { Apr. 1998 (except May -95)  ChA: Chemical Abstracts: Jan. 1997 - Nov. 1998  CTI: Current Technology Index Jan./Feb. 1993 { Jan./Feb. 1994  DAI: Dissertation Abstracts International: Vol. 53 No. 1 { Vol. 56 No. 10 (Apr. 1996)  EEA: Electrical & Electronics Abstracts: Jan. 1991 { Apr. 1998  EI A: The Engineering Index Annual: 1987 { 1992  EI M: The Engineering Index Monthly: Jan. 1993 { Apr. 1998 (except May 1997)  N: Scienti c and Technical Aerospace Reports: Jan. 1993 - Dec. 1995 (except Oct. 1995)  P: Index to Scienti c & Technical Proceedings: Jan. 1986 { May 1998 (except Nov. 1994)  PA: Physics Abstracts: Jan. 1997 { Sep. 1998

1.1 Your contributions erroneous or missing? The bibliography database is updated on a regular basis and certainly contains many errors and inconsistences. The editor would be glad to hear from any reader who notices any errors, missing information, articles etc. In the future a more complete version of this bibliography will be prepared for the genetic algorithms and VLSI research community and others who are interested in this rapidly growing area of genetic algorithms. 1

When submitting updates to the database, paper copies of already published contributions are preferred. Paper copies (or ftp ones) are needed mainly for indexing. We are also doing reviews of dierent aspects and applications of GAs where we need as complete as possible collection of GA papers. Please, do not forget to include complete bibliographical information: copy also proceedings volume title pages, journal table of contents pages, etc. Observe that there exists several versions of each subbibliography, therefore the reference numbers are not unique and should not be used alone in communication, use the key appearing as the last item of the reference entry instead. Complete bibliographical information is really helpful for those who want to nd your contribution in their libraries. If your paper was worth writing and publishing it is certainly worth to be referenced right in a bibliographical database read daily by GA researchers, both newcomers and established ones. For further instructions and information see ftp.uwasa.fi/cs/GAbib/README.

1.1.1 How to cite this report?

The complete BiBTEX record for this report is shown below: @TECHREPORT{gaVLSIbib, KEY = "VLSI", ANNOTE = "*on,*FIN,bibliography /special", AUTHOR = "Jarmo T. Alander", TITLE = "Indexed Bibliography of Genetic Algorithms in Electronics and {VLSI} Design and Testing", INSTITUTION = "University of Vaasa, Department of Information Technology and Production Economics", TYPE = "Report", NUMBER = "94-1-VLSI", NOTE = "(\ftp{ftp.uwasa.fi}{cs/report94-1}{gaVLSIbib.ps.Z})", YEAR = 1995 }

You can also use the BiBTEX le GASUB.bib, which is available in our ftp site ftp.uwasa.fi in directory cs/report94-1 and contains records for all GA subbibliographies.

1.2 How to get this report via Internet? Versions of this bibliography are available via anonymous ftp and www from the following sites: media country site directory le Finland ftp.uwasa.fi /cs/report94-1 gaVLSIbib.ps.Z Finland http://www.cs.hut.fi ja/gaVLSIbib gaVLSIbib.html

ftp www

Observe that these versions may be somewhat dierent and perhaps reduced as compared to this volume that you are now reading. Due to technical problems in transforming LATEXdocuments into html ones the www versions contain usually less information than the corresponding ftp ones. It is also possible that the www version is completely unreachable. The directory also contains some other indexed GA bibliographies shown in table 1.1.

1.3 Acknowledgement The editor wants to acknowledge all who have kindly supplied references, papers and other information on genetic algorithms and VLSI literature. At least the following GA researchers have already kindly supplied their complete autobibliographies and/or proofread references to their papers: Dan Adler, Patrick Argos, Jarmo T. Alander, James E. Baker, Wolfgang Banzhaf, Helio J. C. Barbosa, Hans-Georg Beyer, Christian Bierwirth, Joachim Born, Ralf Bruns, I. L. Bukatova, Thomas Back, David E. Clark, Yuval Davidor, Dipankar Dasgupta, Marco Dorigo, J. Wayland Eheart, Bogdan Filipic, Terence C. Fogarty, David B. Fogel, Toshio Fukuda, Hugo de Garis, Robert C. Glen, David E. Goldberg, Martina GorgesSchleuter, Hitoshi Hemmi, Vasant Honavar, Jerey Horn, Aristides T. Hatjimihail, Mark J. Jakiela, Richard S. Judson, Bryant A. Julstrom, Charles L. Karr, Akihiko Konagaya, Aaron Konstam, John

le

ga90bib.ps.Z ga91bib.ps.Z ga92bib.ps.Z ga93bib.ps.Z ga94bib.ps.Z ga95bib.ps.Z ga96bib.ps.Z ga97bib.ps.Z ga98bib.ps.Z gaAIbib.ps.Z gaALIFEbib.ps.Z gaARTbib.ps.Z gaAUSbib.ps.Z gaBASICSbib.ps.Z gaBIObib.ps.Z gaCADbib.ps.Z gaCHEMPHYSbib.ps.Z gaCONTROLbib.ps.Z gaCSbib.ps.Z gaDBbib.ps.Z gaECObib.ps.Z gaENGbib.ps.Z gaESbib.ps.Z gaFAR-EASTbib.ps.Z gaFRAbib.ps.Z gaFTPbib.ps.Z gaFUZZYbib.ps.Z gaGERbib.ps.Z gaGPbib.ps.Z gaIMPLEbib.ps.Z gaISbib.ps.Z gaJOURNALbib.ps.Z gaLOGISTICSbib.ps.Z gaMANUbib.ps.Z gaMEDITERbib.ps.Z gaNNbib.ps.Z gaNORDICbib.ps.Z gaOPTIMIbib.ps.Z gaOPTICSbib.ps.Z gaORbib.ps.Z gaPARAbib.ps.Z gaPOWERbib.ps.Z gaPROTEINbib.ps.Z gaROBOTbib.ps.Z gaSAbib.ps.Z gaSIGNALbib.ps.Z gaTHEORYbib.ps.Z gaTOP10bib.ps.Z gaUKbib.ps.Z gaVLSIbib.ps.Z

contents GA in 1990 GA in 1991 GA in 1992 GA in 1993 GA in 1994 GA in 1995 GA in 1996 GA in 1997 GA in 1998 GA in arti cial intelligence GA in arti cial life GA in art and music GA in Australia Basics of GA GA in biosciences including medicine GA in Computer Aided Design GA in chemistry and physics GA in control GA in computer science (incl. databases and GP) GA in databases GA in economics and nance GA in engineering Evolution strategies GA in the Far East (Japan etc) GA in France GA papers available via ftp GA and fuzzy logic GA in Germany genetic programming implementations of GA immune systems journal articles GA in logistics GA in manufacturing GA in the Mediterranean GA in neural networks GA in Nordic countries GA and optimization (only a few refs) GA in optics and image processing GA in operations research Parallel and distributed GA GA in power engineering GA in protein research GA in robotics GA and simulated annealing GA in signal and image processing Theory and analysis of GA Authors having at least 10 GA papers GA in United Kingdom GA in VLSI design and testing

Table 1.1: Indexed GA subbibliographies.

R. Koza, Kristinn Kristinsson, D. P. Kwok, Gregory Levitin, Carlos B. Lucasius, Michael de la Maza, John R. McDonnell, J. J. Merelo, Laurence D. Merkle, Zbigniew Michalewics, Melanie Mitchell, David J. Nettleton, Volker Nissen, Ari Nissinen, Tomasz Ostrowski, Kihong Park, Nicholas J. Radclie, Colin R. Reeves, Gordon Roberts, David Rogers, Ivan Santiban~ez-Koref, Marc Schoenauer, Markus Schwehm, Hans-Paul Schwefel, Michael T. Semertzidis, Moshe Sipper, William M. Spears, Donald S. Szarkowicz, El-Ghazali Talbi, Masahiro Tanaka, Leigh Tesfatsion, Peter M. Todd, Marco Tomassini, Andrew L. Tuson, Jari Vaario, Gilles Venturini, Hans-Michael Voigt, Roger L. Wainwright, D. Eric Walters, James F. Whidborne, Steward W. Wilson, Xin Yao, and Xiaodong Yin. The editor also wants to acknowledge Elizabeth Heap-Talvela for her kind proofreading of the manuscript of this bibliography.

Chapter 2

Introduction The table 2.1 gives the queries that have been used to extract this bibliography. The query system as well as the indexing tools used to compile this report from the BiBTEX-database [7] have been implemented by the author mainly as sets of simple awk and gawk programs [8, 9]. string

VLSI electronic channel routing

eld

ANNOTE ANNOTE ANNOTE

class VLSI Electronics Channel routing

Table 2.1: Queries used to extract this subbibliography from the main database.

5

Chapter 3

Statistical summaries This chapter gives some general statistical summaries of genetic algorithms and VLSI literature. More detailed indexes can be found in the next chapter.

type number of items book 1 section of a book 2 part of a collection 4 journal article 97 proceedings article 208 report 7 manual 1 PhD thesis 4 MSc thesis 2 total 326

References to each class (c.f table 2.1) are listed below:

 Channel routing 2 references ([10]-[11])  Electronics 109 references ([12]-[120])  VLSI 214 references ([121]-[334])

Observe that each reference is included (by the computer) only to one of the above classes (see the queries for classi cation in table 2.1; query order gives priority for classes).

Table 3.1: Distribution of publication type.

3.1 Publication type year items year items 1974 1 1975 0 1976 0 1977 0 1978 0 1979 0 1980 0 1981 0 1982 0 1983 0 1984 0 1985 0 1986 1 1987 2 1988 2 1989 3 1990 8 1991 10 1992 11 1993 24 1994 54 1995 68 1996 100 1997 36 1998 6 total 326

This bibliography contains published contributions including reports and patents. All unpublished manuscripts have been omitted unless accepted for publication. In addition theses, PhD, MSc etc., are also included whether or not published somewhere. Table 3.1 gives the distribution of publication type of the whole bibliography. Observe that the number of journal articles may also include articles published or to be published in unknown forums.

3.2 Annual distribution Table 3.2 gives the number of genetic algorithms and VLSI papers published annually. The annual distribution is also shown in g. 3.1. The average annual growth of GA papers has been approximately 40 % during almost the last twenty years.

Table 3.2: Annual distribution of contributions.

7

3.3 Classi cation

3.4 Authors Table 3.4 gives the most productive authors.

Every bibliography item has been given at least one describing keyword or classi cation by the editor of this bibliography. Keywords occurring most are shown in table 3.3.

total number of authors 460 Arslan, T. 17 Drechsler, Rolf 13 Becker, Bernd 11 Mazumder, Pinaki 11 2 authors 9 5 authors 8 3 authors 7 10 authors 6 11 authors 5 9 authors 4 21 authors 3 74 authors 2 320 authors 1 Table 3.4: The most productive genetic algorithms and VLSI authors.

3.5 Geographical distribution The following table gives the geographical distribution of authors, when the country of the author was known. Over 80% of the references of the main database are classi ed by country. VLSI 118 electronics 96 VLSI design 70 CAD 44 testing 21 parallel GA 21 layout design 18 comparison 16 engineering 14 routing 12 genetic programming 11 others 649

Table 3.3: The most popular subjects.

country abs % Total 325 100.00 United States 107 32.92 United Kingdom 47 14.46 Germany (incl. DDR) 33 10.15 Japan 27 8.31 India 22 6.77 Italy 14 4.31 Unknown country 12 3.69 Canada 9 2.77 Saudi Arabia 7 2.15 Australia 4 1.23 Czech Republic 4 1.23 Denmark 4 1.23 Taiwan R.o.C. 4 1.23 Kuwait 3 0.92 South Korea 3 0.92 Brazil 2 0.62 China (incl. Hong Kong) 2 0.62 Finland 2 0.62 France 2 0.62 Poland 2 0.62 Spain 2 0.62 Switzerland 2 0.62 The Netherlands 2 0.62 Byelorussia 1 0.31 Greece 1 0.31 Romania 1 0.31 Singapore 1 0.31 Slovak Republic 1 0.31 Thailand 1 0.31 Ukraina 1 0.31

Table 3.5: The geographical distribution of the authors.

6 Genetic algorithms and VLSI dd d d d d d d d d

1000 number of annual papers (log scale) 100

t dd t dd t t d t d d d d d d tt d d dd 10 t d t dd d d dd t d d d d tt d d d

1d

dd

1960

t

1970 year 1980

t

1990

-

2000

Figure 3.1: The number of papers applying genetic algorithms and VLSI ()  = total GA papers. Observe that the last two years are most incomplete in the database.

3.6 Conclusions and future The editor believes that this bibliography contains references to most genetic algorithms and VLSI contributions upto and including the year 1998 and the editor hopes that this bibliography could give some help to those who are working or planning to work in this rapidly growing area of genetic algorithms.

Chapter 4

Indexes 4.1 Books

IEEE Transactions on Circuits and Systems { I: Fundamental Theory and Applications, IEEE Transactions on Computer Aided Design and Integrated Circuits Systems, IEEE Transactions on Computer Aided Design Integr. Circuits Syst., IEEE Transactions on Computer Aided Design of Integrated Circuits, IEEE Transactions on Computer-Aided Design, [60]

The following list contains all items classi ed as books. Evolutionary Algorithms for VLSI CAD,

[293]

[224]

[283]

[248]

[294, 302,

4.2 Journal articles

308, 323]

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,

[163, 165,

The following list contains the references to every journal article included in this bibliography. The list is arranged in alphabetical order by the name of the journal.

244, 299, 313, 330]

IEEE Transactions on Computing, IEEE Transactions on Evolutionary Computing, IEEE Transactions on Industrial Electronics, IEEE Transactions on Semiconductor Manufacturing, [205]

[280]

[66]

ACM Computer Surveys, ACM Trans. Des. Autom. Electron. Syst. (USA), Acta Electronica Sinica, Annals CIRP, Applied Physics Letters, Archiv fur Elektrotechnik, Bulletin of Faculty of Engineering, Tokushima University (Japan), Electronics Letters,

IEEE Transactions on Systems, Man, and Cybernetics,

[326]

[264]

[160]

IEEE Transactions on Very Large Scale Integration VLSI Systems, IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, Int. J. Syst. Sci. (UK), Integration, the VLSI Journal, International Journal of Circuit Theory and Applications,

[44]

[220]

[115]

[29]

[138, 11, 118]

[109, 111]

[93]

[147, 327]

[329]

[134, 137, 144, 155, 45, 76, 235, 251,

[38]

International Journal of Computer Aided VLSI Design,

253, 92, 281, 105, 116]

Elektron. Ind. (Germany), Evolutionary Computation, IEE Proc Devices Syst, IEE Proc., Comput. Digit. Tech. (UK), IEE Proceedings E: Comput. Digit. Tech., IEE Proceedings, Computers and Digital Techniques,

[222,

97]

[56]

[298]

International Journal of Electronics,

[157]

[122, 13, 146, 164, 168,

80, 317]

[200]

International Journal of Heat and Mass Transfer, International Journal of Manufacturing Systems, J. Circuits Syst. Comput. (Singapore), J. Jpn. Soc. Artif. Intell. (Japan), J. Korea Inst. Telemat. Electron. (South Korea), J. VLSI Signal Process, Microelectron Reliab, Microelectron, J. (UK),

[69]

[292]

[14] [63]

[254]

[140,

[219]

36]

IEEE Potentials, IEEE Proc. Comput. Digital Tech., IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (USA), [110]

[214]

[286]

[96, 102]

[263]

[274]

11

[100]

Microelectron. J., Microelectron. J. (UK), Microprocessors and Microprogramming, Midwest Symp Circuits Syst, PARS-Mitteilungen, Texas Instrument Technology Journal, The International Journal of Advanced Manufacturing Technology, Trans. Inf. Process. Soc. Jpn. (Japan), Trans. Inst. Electr. Eng. Jpn. C (Japan), Trans. Soc. Instrum. Control Eng. (Japan), Transaction of the Institute of Electronics, Inform, Transaction of the Institute of Electronics, Information and Communication Engineers A (Japan), Transactions of ASME, Journal of Electronics Packaging, [25]

[94]

[123, 171]

[189]

[154]

[305]

[106]

[215]

[184, 268] [195]

[232]

[130, 119]

[114]

Transactions of the Institute of Electrical Engineers of Japan C, VLSI Design, [17]

[133, 197, 228, 243]

total 97 articles in 58 series

4.3 Theses The following two lists contain theses, rst PhD theses and then Master's etc. theses, arranged in alphabetical order by the name of the school.

4.3.1 PhD theses

City University,

[26]

The Pennsylvania State University, University of Cincinnati, University of Waterloo,

[132]

[158]

[161]

total 4 thesis in 4 schools

4.3.2 Master's theses This list includes also \Diplomarbeit", \Tech. Lic. Theses", etc. Hochschule der Bundeswehr Munchen, Universitat Kaiserslautern,

[112]

total 2 thesis in 2 schools

[117]

4.4 Report series The following list contains references to all papers published as technical reports. The list is arranged in alphabetical order by the name of the institute. Electrotechnical Laboratory, Friedrich-Alexander-Universitat Erlangen-Nurnberg, Santa Clara University, University of Michigan, University of Virginia, Universitat Erlangen-Nurnberg, Universitat Frankfurt, [334]

[322]

[316]

[311]

[295]

[139]

[127]

total 7 reports in 7 institutes

4.5 Patents The following list contains the names of the patents of genetic algorithms and VLSI. The list is arranged in alphabetical order by the name of the patent. 

none

4.6 Authors The following list contains all genetic algorithms and VLSI authors and references to their known contributions. Abraham, Jacob A., Agarwal, Reena, Ahmad, Imtiaz, Ahn, Hee II, Ajjarapu, V., Akhmetov, D. F., Albanna, Z., Ali, Hesham H., Allred, Lloyd G., Almaini, A. E. A., Alpert, C. J., Amaral, Jose Nelson, Andre, David,

[125, 224, 319]

[121]

[200, 286]

[182]

[107]

[73]

[107]

[189]

[108]

[25, 36, 45]

[49]

[160, 287]

[59, 75, 79,

[161]

[134, 172, 181,

247, 251, 253, 88, 256, 259, 276]

[305]

[297, 298]

[308, 309, 310]

[290]

[13]

[291]

[109]

[162]

[127, 145, 166,

46, 47, 207, 209, 77, 238, 266, 272]

Bennett III, Forest H.,

[75, 101, 103,

104]

Bennett III, Forrest H., Benten, M. S. T., Benten, Muhammad S. T.,

[59, 79, 87]

[84]

[122, 146,

176, 199, 201]

Bhasker, Jayaram, Bhatia, N., Bialko, M., Billina, S., Bland, I. M., Blickle, Tobias,

[13, 41, 78,

Brandt, H., Brezina, T., Bright, M. S.,

[20]

[82]

[50, 204, 235,

256]

190, 50, 204, 217, 234, 235, 242,

Ashmore, B., Aylor, J. H., Banerjee, P., Banzhaf, Wolfgang, Barclay, Peter J., Bassett, Steve, Bassus, R. C., Bazylevych, Roman P., Becker, Bernd,

[45]

250]

87, 101, 104]

Areibi, Shawki, Arslan, T.,

Bourset, F., Bradbeer, Peter V. G.,

[165]

[93]

[72]

[36]

[76]

[223, 67]

Budzisz, H., Cabrasawan, Feb J., Catania, V., Chakrabarti, P. P., Chakravarty, Sreejit, Chan, Heming, Chan, Shu-Park, Chandrasekaran, S., Chandrasekharam, R., Chang, R.-I., Chattopadhyay, S., Chaudhuri, P. P., Chaudhury, S., Chen, C. Y. R., Chen, Ching-Dong, Chen, T., Cheng, K. T., Cheung, P. Y. K., Cho, Tsu Won, Choi, Kiyoung, Chung, C. Y., Clemens, G., Cluitmans, L. J. M., Cohoon, James P.,

[105]

[183]

[213]

[68]

[327]

[316, 317]

[96]

[123, 147, 292]

[137]

[205, 282]

[205, 282]

[292]

[286]

[163]

[197]

[278]

[84]

[182]

[100]

[149]

[56]

[185]

[196, 212,

[60]

[124]

[236, 248,

257, 258, 260]

Curatelli, F., Daalder, J., Date, H.,

[126] [233] [271] [14] [165, 200, 286] [73] [127, 145,

166, 46, 47, 207, 209, 77, 238, 85,

266, 281, 283]

[18]

293, 294, 295, 296, 297, 298, 299]

Contini, Fabrizio, Coon, Brett W., Corno, Fulvio,

Davis, Mike, deAbreuMoreira, D., Dediu, A. Horia, Devarakonda, R., Dhodhi, Muhammad K., Dote, Y., Drechsler, Rolf,

[164]

[206]

[215]

Dunlap, Frank, Eklund, P. W., Elias, John G., Engst, Norbert, Esbensen, Henrik,

[101] [206] [126] [322] [127, 156,

159, 237, 249, 264, 270, 300]

Eshelman, Larry J., Falck, E., Fekadu, Adhanom A., Feldhousen, E. L., Femia, N., Fiorito, N., Frenzel, James F., Frye, Robert C., Furuhashi, Takeshi, Furuya, Tatsumi, Gardner, Julian W., Garis, Hugo de, George, Suju M., Geraci, M., Gerlach, W., Ghose, S., Ghosh, Joydeep, Gilbert, Daphne J., Girard, P., Glasmacher, Klaus, Glinianowicz, J., Gockel, Nicole,

[54] [109] [113] [297, 298] [95, 95] [183] [110] [222] [17] [333, 334] [113] [333, 334] [148] [304] [109] [213] [160, 287] [277] [208] [303, 306] [72] [166, 46, 47,

207, 209, 77, 238, 85, 266]

G"ockel, Nicole, Gold, Sonke-Sonnich,

[281] [322]

Graf, J., Gramatova, Elena, Greenstein, Gary S., Grewal, G. W., Grimbleby, J. B., Hagen, L. W., Haikarainen, Sakari, Hajj, Ibrahim N., Han, Seung-Kee, Han, Seung-Soo, Handa, Keiichi, Handa, K., Hansdah, R. C.,

[111]

[179]

[15, 263]

[167, 279]

[27]

[49]

[51]

[180, 229]

[182]

[81, 97]

[28]

[184]

[10, 151, 174,

288, 289]

Hatayama, K., Haupt, R., Hayashi, T., Hegde, Shailesh U., Hegde, U., Heijligers, M. J. M., Hemmi, Hitoshi,

[141, 215]

[239]

[141]

[295, 299]

[305]

[185]

[12, 19, 21,

23, 24]

Hering, K., He, Axel, Hidalgo, J. I., Hielscher, Frank H., Higuchi, Tetsuya, Higuchi, T., Hill, A. M., Hines, Evor L., Hirata, H., Hirst, Tony, Holm, John G., Holt, G., Holt, Glenn, Honiden, S., Horrocks, D. H.,

[239]

[306, 112]

[94]

[165]

[333, 334]

[226]

[128]

[113]

[195, 268]

[52]

[22]

[53]

[265]

[184]

[253, 256, 89,

90, 259]

Horrocks, David H.,

[50, 234, 247,

[137]

[92]

[301, 302]

[331]

[307]

[14]

[129]

[226]

[333, 334]

[130]

[200]

[82]

[321]

[210]

[240]

Keim, Martin, Kelly, Gary E., Kesper, M., Khalifa, Y. M. A.,

Khalifa, Yaser M. A., Khamisani, W., Khoo, L. P., Kim, Yongjoo, King, R.-M., Kirsch, Karlheinz, Kita, H., Kling, R.-M., Knight, John P., Koakutsu, S., Koza, John R.,

[86]

[140, 328]

[106]

[100]

[308, 309]

[139, 154]

[141]

[310]

[320]

[195, 268]

[59, 75, 79,

87, 101, 103, 104]

[143]

[211]

[290]

[285]

[56]

[29]

[57]

[33]

[64]

[185]

[278]

[186]

[316, 317]

[203]

[261]

[297, 298]

[51]

[223]

[49]

[226]

[135]

[128]

[102]

[187]

[168]

[59, 75, 79,

87, 101, 104]

86]

Horsky, J., Hosticka, B. J., Hsiao, M. S., Hsiao, Michael S.,

Hsiao, P.-Yung, Hsu, Chen-Chien, Hsu, Y. C., Hu, Yu Hen, Hulin, Martin, Humphrey, J. A. C., Hurson, A. R., Iba, H., Iba, Hitoshi, Inoue, Inoue, Ismaeel, A. A., Ivanov, A., Ivey, Peter A., Iwamoto, Takashi, Jain, A., Jakob, W., Jakumeit, J., Jakumeit, Jurgen, James-Roxby, Philip B., Jantarang, Sujate, Jess, J. A. G., Jiang, Y. M., Jin, Hong Lan, Jin, Lin-Ming, Johnson, A. D., Johnson, Anthony D., Johnson, B. W., Jokinen, Hannu, Kaeslin, Hubert, Kahng, A. B., Kakazu, Y., Kang, S. M., Kang, Sung-Mo, Kannan, J., Kapoor, B., Karafyllidis, Ioannis, Keane, Martin A.,

[266, 272]

[108]

[321]

[89, 90]

Krejsa, Jir, Krieger, R., Krstic, A., Kruiskamp, Wim, Kuga, Shinipei, Kuh, Ernest S., Kurbel, Karl, Kyuma, Kazuo, Lai, Y. T., Lanchares, J., Landrault, C., Lang, K. J., Larcombe, Steven P., Lavenier, Dominique, Lee, K. L., Lee, Michael A., Lee, Terry, Lee, Yuh-Sheng, Leenaerts, Domine, Lemoine, Eric, Lesniak, Joanna, Leu, Ming C., Leung, S. H., Levitt, Jeremy R., Liao, Jianmin, Lienig, Jens,

[82]

[272]

[278]

[30, 38]

[28]

[237, 249, 264]

[169]

[290]

[332]

[94]

[208]

[58]

[211]

[214]

[40]

[270]

[180, 229]

[163]

[30, 38]

[39]

[18]

[114, 115]

[149]

[170]

[70]

[131, 20, 157,

212, 241, 254, 269, 280]

Lim, H. T., Lin, Y. L., Lin, Youn-Long,

[40]

[301, 302]

[163]

Liu, B. D., Liu, Luoping, Liu, Xingzhao,

[332]

[126]

[138, 11, 329,

118, 119, 120]

Lohn, Jason, Luchian, Henri, Ly, Tai A., Majhi, A. K., Makki, R. Z., Malgeri, M., Mandal, C. A., Mao, Chi-Yu, Martin, Raul San, Martin, Worthy N., Massoumi, M., May, Gary S., Mazumder, Pinaki,

[101]

[13]

[330]

[171]

[133]

[183]

[213]

[331]

[320]

[295, 296, 299]

[218]

[81, 97]

[140, 156,

311, 312, 313, 323, 324, 325, 326,

327, 328]

Mazumder, P., McConnell, Roderick, Megson, G. M., Meinzer, S., Menozzi, Roberto, Merceron, David, Michalewicz, Zbigniew, Mihaila, D., Miller, J. F.,

[194]

[214]

[76]

[56]

[60]

[39]

[133]

[271]

[142, 36, 69,

80]

Miller, Julian F.,

[13, 31, 41,

55, 78, 250]

Miyanaga, Yoshikazu, Mizoguchi, Jun'ichi,

[186]

[12, 19, 21,

23, 24]

Mlynski, Dieter A., Mohan, S., Moon, Byung-Ro, Moraga, Claudio, Moraga, C., Moreira, D. de Abreu, Mosca, R., Mowchenko, Jack T., Muddappa, S., Mudge, Trevor, Nakayama, T.,

Narasimhan, R., Nassar, K., Natsume, K., Negoita, Mircea Gh., Nelson, K. M., Nemec, Viktor, Ng, S. C., Nguyen Bui, Thang, Niermann, Thomas M., Niwa, Tatsuya, Noteboom, Ron, O'Dare, M. J.,

[188]

[176, 199]

[209, 238]

[271]

[14]

[32]

[56]

[216]

[219]

[149]

[150]

[311, 312, 313]

[132]

[71, 246]

[231]

[61]

[236]

[330]

[133]

[178]

[290]

Patnaik, L. M.,

[314]

[252]

[15, 263]

[63]

[333, 334]

[285]

[189]

[96, 102]

[134, 172,

[173]

[206]

[272]

[135]

[116]

[106]

[219]

[314]

[139, 154, 322]

[304]

[322]

[50, 234, 247,

[62]

[129]

[293, 294]

[210, 263]

[15, 22, 175,

192, 229, 240]

[83]

Prinetto, P., Pudelko, Gregor, Queipo, N., Quinte, A., Rahmani, A. T., Rahmani, Adel Torkaman, Rajarajan, N., Rajasekharan, M., Rajesh, V., Ramachandran, V., Raman, S., Raman, Srilata, RamBabu, P., Ranganathan, N., Rao, B. B. Prahlada,

[136, 152]

[215]

253, 256, 259]

Padgett, M. L., Pakzad, S., Paris, William D., Patel, J. H., Patel, Janak H.,

[236, 248,

257, 258, 260]

190, 217, 242, 251, 88, 276]

Ohmori, Kenji, Ohmori, K., Okmen, C., Olson, Eric, O'Neill, A. W., Ong, N. S., Ono, N., Ono, Norihiko, Opaterny, Thilo, Orlando, P., Ost, Alexander, Ozdemir, E.,

Prinetto, Paolo,

[10, 171, 174,

191, 220, 288, 315]

Patnaik, Lalit M., Peters, B. A., Piazzi, Aurelio, Pierzchala, Marian, Placer, J., Pomeranz, Irith, Pookaiyaudom, Sitthichai, Pravossoudovitch, S., Predergast, David J.,

[228]

[63]

[60]

[42]

[218]

[43, 267, 273]

[64]

[208]

[211]

[171]

[191, 220]

[148]

[230]

[10, 151, 174,

288, 289]

Rao, Vasant B., Raudensky, Miroslav, Ravi, S. S., Ravikumar, C. P., Rebaudengo, Maurizio,

[318]

[82]

[188]

[243, 252, 255]

[136, 152,

236, 244, 248, 257, 258, 260]

Rebaudengo, M., Reddy, S. M., Reddy, Sudhakar M., Reinartz, Karl Dieter, Reorda, M. S., Reorda, Matteo Sonza, Richards, Dana S., Richert, P., Rietman, Edward A., Rinderle, J., Robertson, G. I., Robinson, Gordon M., Rodanski, Benedykt, Rodriguez, B., Rogenmoser, Robert, Ro Moon, Byung, Ronald, Simon, Rosenkrantz, D. J., Roy, S.,

[153, 221]

[140, 267, 328]

[43, 273]

[322]

[221]

[244, 257, 258]

[296, 299]

[321]

[222]

[117]

[80]

[26, 37]

[42]

[208]

[223]

[150]

[202]

[188]

[205]

Roy, U., Rudnick, E. M., Rudnick, Elizabeth M.,

[70]

[210, 263]

[15, 22, 175,

192, 229, 240]

Russo, Marco, Saab, Daniel G.,

[183]

[125, 22, 224,

319]

Saab, Youssef G.,

[125, 224,

318, 319]

Sagahyroon, A., Sait, Sadiq M.,

[218]

[122, 146,

176, 193, 199, 201, 225, 274]

Sakamoto, Akio,

[138, 11, 329,

118, 119, 120]

Sakanashi, H., Sanchez, J. M., Sathiyanarayanan, K., Saxena, Ashutosh, Saxena, V., Schaer, J. D., Schaftner, Christoph, Schnecke, Volker, Schneider, Bernd, Scholles, M., Schwarz, Josef, Schwarz, M., Schwehm, Markus, Seals, R. C., Sengupta, I., Sen Gupta, Indranil, Shahookar, Khushro,

[226]

[34, 94]

[96, 102]

[148]

[243, 255]

[54]

[322]

[177, 227, 245]

[169]

[321]

[216, 98, 284]

[321]

[139, 154, 322]

[16, 65]

[93]

[121]

[140, 323,

[194]

[40]

[138, 11, 329,

118, 119, 120]

Shimohara, Katsunori,

[12, 19, 21,

23, 24]

Singer, S., Singer, Steven, Singh, Kirti, Sivakumar, V., Slama, L., Soldek, J., Sonza Reorda, Matteo, 236, 248, 260]

[153]

[304]

[95, 95]

[167]

[178]

[179]

[165]

[123, 147, 292]

[203, 261]

[66]

[277]

[232]

[333, 334]

[329, 119]

[201]

[195, 268]

[67]

[162]

[211]

[68]

[168]

[67]

[48, 74]

[31, 41, 55,

78, 250]

Thomson, P.,

[99]

[275]

[148, 169]

[96, 102]

[82]

[35]

[136, 152,

Thulasiraman, K., Tjuji, B., Tochinai, Koji, Tsai, F. S., Tse, Kai-Ming, Tumer, Kagan, Turton, B. C. H., Tyagi, Akhilesh, Tyagi, A, Uchikawa, Yoshiki, Valtonen, Martti, Valtonen, Martti, Vanetsky, Larry, Varanelli, James M., Vasallo, G.,

Veiluva, E., Vemuri, Ram Mohan, Vemuri, R.,

[136]

[158]

[144, 144,

155, 155]

[228, 315]

[142, 36, 69,

80]

324, 325, 326, 327, 328]

Shahookar, K., Shim, M. S., Shimamoto, Takashi,

Sonza Reorda, M., Sorbello, F., Spagnuolo, G., Srinivas, M., Stacey, D. A., Stanley, Timothy J., Stefanovic, Juraj, Storer, Robert H., Subramanian, S., Sun, Rongchung, Surmann, Hartmut, Takhar, Jasbir S., Tamamoto, H., Tanaka, Toshio, Taniguchi, N., Tanvir, Shahid, Tazawa, I., Teich, Jurgen, Teliuk, Taras M., Thacker, Neil A., Thadikaran, Paul, Thanailakis, Adonios, Thiele, Lothar, Thompson, Adrian, Thomson, Peter,

[131, 157, 254]

[143]

[186]

[301, 302]

[92]

[160, 287]

[181]

[265]

[53]

[17]

[51]

[91]

[275]

[196]

[304]

Vijaykrishnan, N., Villmann, Th., Vinod, V. V., Vocca, G., Vornberger, Oliver, Wagemann, H. G., Walczowski, L. T., Walter, Thomas, Wang, B. H., Wang, Chi-Hsu, Wang, L. Y., Wang, W. J., Wang, Wenjun, Wang, W., Wang, Xiao-Dong, Wei, Tian, Wesselkamper, T. C., West, Christine M., Whapshott, G. F., Wilson, T. C., Winchell, Michael, Wojcikowski, M., Wolf, Hans G., Wong, Hermean, Wu, A. C.-H., Xieting, Ling, Yan, Jin-Tai, Yanushkevich, S., Yeh, M. Y., Yokoyama, H., Yoshikawa, T., Youssef, Habib,

[230]

[239]

[123, 147]

[95, 95]

[177, 227, 245]

[111]

[233, 61]

[322]

[40]

[92]

[332]

[231]

[71]

[246]

[197]

[44]

[18]

[262]

[16]

[167, 279]

[291]

[72]

[83]

[114, 115]

[163]

[44]

[198]

[35]

[332]

[232]

[17]

[176, 193,

199, 201, 225, 274]

Zhuang, N., Zimmermann, Gerhard, Zorian, Y.,

[25, 45, 84]

[303, 306]

[143]

total 325 articles by 460 dierent authors

4.7 Subject index All subject keywords of the papers given by the editor of this bibliography are shown next. agents, analysing GA parallel, application, VLSI, applications electronics, in electronics, real-time, arti cial intelligence, assembly electronics,

exible, planning, assembly line balancing, assembly planning, ATPG, automata nite state, automaton nite state, bin-packing 2D, Boolean functions,

[61, 233]

[98]

[324, 307]

[292]

[281]

[40]

[206]

[32]

[228]

[58]

[54]

[258]

[63]

[223]

[106]

[271]

[54]

[317, 330,

[114, 115]

[190, 260]

122, 144, 146, 155, 171]

traditional methods, computational geometry, control motion, converters, crossover comparison of 13 types, cycle, DARWIN, data ordering problem, design combinatorial circuits, printed circuit boards, VLSI,

[36]

[300]

[36]

[45, 207, 55,

288, 291, 320, 329, 118, 330, 331, 130, 18]

[13]

[17, 19, 21,

[11]

[207]

[30, 38]

[301, 302,

318, 290, 287, 312, 317, 292, 313,

330, 332, 128, 148, 159, 174, 283]

[79]

[87]

[318] [114, 115, 54,

63]

CAD, channel routing, circuit design,

[112] [118, 119] [53, 72, 87,

103]

circuit optimization, circuit simpli cation, circuit simulation, cooling, design,

[51] [64] [91] [14] [119, 16, 50,

[13, 175, 34,

electron density in semiconductors, evolution, fault tolerance, FET, HDL, HDL programs, layout design, MOSFET, multivalued circuits, network synthesis, NiCd batteries, op amp, op amps, part placement, PBC layout, PCB, [29]

[317]

dierential GA, digital circuits hazards, digital electronics, optimization, Reed-Muller, state machines,

[89, 90]

94, 100]

[74]

[48]

[60]

[19, 21, 23, 24]

[69]

[118]

[294, 325,

329, 128, 212]

23, 24, 59, 77]

[28, 86, 95,

65, 68, 69, 71, 76, 78, 80, 251, 93,

[85]

[295, 112,

[30, 38]

35, 39, 41, 43, 46, 47, 58, 205, 55,

[30, 38]

[13]

[18]

analogue, ASIC, assembly,

digital,

[95]

[322]

[107, 298, 317,

56, 67, 92, 105]

[73]

[133]

[113]

101]

[147]

[181]

[289]

electronics 3-valued transistor, ampli ers, analog,

[49]

[85]

EDGA, electronic nose, electronics,

111, 12, 137, 42, 49, 84, 96, 102]

[85, 103]

[327]

316, 107, 299, 306, 327, 300, 303,

CAD/ electronics, cellular automata,

chromosome 2D bitmap, circuit design, circuit partitioning, clique cover, comparison, branch and bound, evolutionary programming, gradient descent, hill climbing, in VLSI testing, Monte Carlo, mutation, simulated annealing, [327]

Reed-Muller expansions, CAD,

IC, opamps, VLSI,

[314, 120,

131, 10, 11, 157, 203, 261]

250]

CAD digital circuits, electronics,

channel routing,

[16]

[61]

[57]

[71]

[108]

[27]

[66]

[251]

[275]

[31]

[25, 45]

[36]

[75]

[104] [32]

[98]

[162]

PCB assembly, power, semiconductor [81]

sensoring, silicon processing, test generation, testing, tolerances, transistor arrays, transistors, electronics testing, electronics?, engineering computer, electronic, electronics,

[17, 106]

[73]

manufacturing, [26, 37]

[97]

[15, 22]

[82, 88]

[44]

[83]

[223]

[108]

[52, 70]

[25]

[162]

[297, 109, 110,

120, 122, 146, 20, 32, 85, 117]

power, radio, engineering design, evolution strategies, exponential tting, FEM, lters, nite state machines,

oorplanning, formal languages, FPGA, functions Boolean, fuzzy systems, FuzzyART, GALLO, GAPE, GASBOR, GASP, GATE, GATTO, generations 100, genetic programming,

[107]

[60]

[70]

[109, 111, 117]

[108]

[26, 37]

[87]

[123]

[274]

[322]

[39]

genetic programming decision diagrams, Genie, GenNETS, graph coloring, graphs, partitioning, hardware, hardware design, hybrid, GRASP, hill-climbing, neural networks, simulated annealing,

[226]

[294]

[333]

[292]

[292]

[132, 150]

[321, 271]

[330]

[132]

[161]

[164]

[148]

[156, 164,

169, 179]

tabu search, image processing, fractals, immune systems, implementation C, Hypercube, MasPar, MIMD, Occam, transputers, VLSI, interval arithmetics, intervals, layout design,

[161, 55]

[108]

[322]

[195, 268]

[299]

[299]

[322]

[289]

[216]

[289, 216]

[181]

[95]

[44]

[295, 299,

327, 305, 312, 313, 331, 130, 177,

[69]

[270]

[99]

53, 61, 221, 265, 98]

layout design VLSI,

[310, 308,

140, 245]

[244]

[299]

[254]

[325]

[298]

[136, 248]

[116]

[124, 23, 58,

59, 75, 79, 87, 101, 103, 104]

load cells, LOCSTEP, logic, logic design, LSI design, macro cell layout, macro cellslayout design, manufacturing

[26, 37]

[43]

[13]

[282]

[28]

[322]

[198]

assembly, assembly planning, electronics, maximal clique, MCM partitioning, meta GA, microprogramming, multi level logic circuits, mutation, neural networks, electronic nose, modeling, optoelectronic, training, node partitioning, OBDD, optics IR, optimization digital electronics, multi-objective, packaging 3D, parallel GA,

[54]

[106]

[63]

[292]

[220]

[323, 324, 326]

[183]

[34]

[10]

[113, 333, 81]

[33]

[97]

[116]

[116, 110]

[292]

[272]

[108]

[31]

[270]

[211]

[295, 296,

299, 311, 288, 289, 322, 126, 139,

154, 169, 178, 181, 216, 221, 241, 269, 98, 280]

parallel GA adaptive, workstation network, permutation crossover, physics solid state, thermal, PLA, placement, placement optimization, planning electronics, population size 30,

[245]

[312]

[140]

[29]

[14]

[122, 146]

[294]

[233]

[17]

[116]

problem state assignment, production economics quality, random number generators systolic, Reed-Muller expansion, Reed-Muller functions, reliability, redundancy, review analogue circuit design, electronics, routing,

telecommunications, test pattern generation, testing, combinatorial circuits, electronics, logic, test pattern generation, VLSI,

[285]

[41]

[90]

[62]

[329, 119,

120, 159, 83, 254]

[20]

[202]

[304, 163,

[66]

[172]

[297, 298,

VLSI analysis, CAD, channel routing,

[156]

[322, 330,

[202]

[202]

[202]

[95]

[113, 82]

[26, 37]

[60]

[50, 204, 235,

256]

[196]

[323, 326]

CMOS, CMOS transistors, design,

[193]

[108]

[243]

[322, 132, 216]

[296, 321, 303,

[218]

[316, 290]

[138, 174,

[199]

[230]

[212]

[28]

circuit partitioning,

oorplan,

oorplan area, gate matrix layout, high level synthesis, high-level synthesis, layout,

[284]

[195, 244, 268]

[153]

[121]

[330]

[165]

[295, 308,

327, 305, 322, 265]

macro cell layout, macro cells, macrocells, MCM, module orientation, optimization, partitioning, placement, power, Reed-Muller expressions,

[156]

[159]

[137]

[126, 129,

130, 132, 138, 146, 157, 162, 163,

187, 189, 192, 193, 194, 197, 198, 199, 200, 201, 202, 203, 204, 207, 211, 212, 213, 214, 220, 225, 226, 227, 230, 233, 234, 235, 237, 239, 240, 243, 246, 247, 249, 253, 256, 259, 274, 279, 281, 282, 283]

macrocell layout, manufacturing, MCM, multichip modules, power optimization, routing,

[289, 131,

[144, 155]

[223]

[196]

[191]

[142]

[168]

[293]

[278]

[127,

145]

routing,

[301, 304,

314, 332, 280]

[188]

scan path, software, standard cell, standard cell placement, standard-cell placement,

[252]

[201]

[183]

[142, 163, 250]

[326]

[334]

[173]

[309, 328,

161, 245, 270]

[161]

[184]

[139, 154]

[246]

164, 167, 171, 173, 177, 182, 185,

design?, dsign, fault tolerance,

oorplanning, FPGA, HDL, high-level synthesis, layout design,

VLSI design cell placement, channel routing, 151, 219, 261]

209, 238]

167, 181, 279]

simulated annealing, standard cell placement, standard cells layout, standard-cell placement, SURGEN, survey VLSI design, tabu search,

135, 140, 147, 150, 160, 174, 186, 286, 216, 221, 231, 255, 271, 272]

307, 312, 291, 313, 331, 333, 128]

182, 189]

JSS, multiprocessor, school bus, sensitivity analysis, sensoring, sensors force, signal processing circuit modeling, hardware,

text book VLSI design, thermal pro les, TOGAPS, TSP, VLSI,

[323, 324, 299,

300, 288, 320, 122, 123, 124, 133,

232, 242, 243, 248, 255, 266, 273]

[96]

267, 275, 276, 277, 285]

VLSI design,

319, 134, 190, 205, 215, 217, 228,

[102]

rule based systems fuzzy, SAGA, scheduling,

251, 257, 258, 260, 262, 263, 266, [68]

[43]

[80]

[315, 125,

136, 141, 143, 152, 172, 175, 179,

[99]

[76]

[202]

180, 200, 208, 210, 224, 229, 236,

[147]

[222]

multi-chip modules, TSP, VLSI,

standard cell placement, testing,

[11]

[287]

[176]

[311,

148, 169]

switchbox routing, VLSI design/Reed-Muller expressions, VLSI design?, VLSI desin MCM, VLSI?, [254]

[306]

[222]

[191]

[158]

[235, 256]

[302, 241, 269]

[166]

[170, 206]

[264]

[149, 178]

4.8 Annual index The following table gives references to the contributions by the year of publishing. 1986, 1987, 1988, 1989, 1990, 1991, 1992, 1993,

[293] [294, 310]

183, 37, 184, 185, 186, 187, 38, 39, 40, 41, 188, 189, 190, 42, 43, 191, 192, 193, 194, 195, 196, 44, 197, 198, 199, 45, 200, 46, 201, 47, 202, 58, 286]

[302, 308, 318] [296, 297, 112, 309, 316, 323, 324, 325]

[25, 160, 161, 162, 163, 164, 165, 166, 26, 167, 27, 28, 29, 168, 30, 169, 170, 171, 31, 32, 172, 173, 174, 33, 175, 176, 34, 177, 35, 178, 179, 180, 181, 182, 36,

[295, 301]

1996,

[107, 290, 298, 299, 304, 306, 311, 321,

[203, 48, 49, 50, 204, 205, 206, 207, 208, 209, 51, 52, 53, 210, 54, 55, 56, 57, 59, 211, 212, 213, 214, 60, 61, 215, 216, 217, 62, 63, 218, 64, 219, 220, 221,

326, 327]

222, 223, 224, 225, 226, 227, 65, 228, 66, 229, 67, 68, 69, 70, [108, 287, 109, 300, 303, 305, 307, 312,

230, 231, 71, 72, 73, 232, 233, 74, 234, 75, 76, 235, 236, 77,

116, 317, 319]

237, 238, 239, 240, 78, 79, 241, 242, 243, 244, 80, 81, 245, 82, 246, 83, 84, 247, 248, 85, 249, 250, 251, 252, 253, 86, 87, [288, 289, 291, 292, 110, 111, 113, 114,

254, 88, 255, 256, 257, 89, 258, 90, 259, 260]

115, 313, 314, 315, 320, 322, 328, 329, 118, 119, 120, 330, 331, 332, 333, 334]

1994,

1995,

[121, 122, 123, 124, 125, 126, 127, 12,

1997,

128, 129, 130, 13, 131, 132, 133, 134, 135, 136, 14, 137, 10,

[91, 261, 92, 262, 263, 264, 265, 266, 267, 93, 268, 269, 94, 270, 95, 95, 271, 272, 273, 96, 97, 274, 275, 98, 99, 276, 277, 278, 100, 279, 101, 280, 102, 281, 103, 104]

15, 138, 139, 16, 140, 141, 142, 143, 144, 11, 17, 145, 146, 18, 147, 148, 19, 149, 20, 21, 150, 151, 152, 153, 22, 154, 155, 156, 23, 157, 24, 158, 159]

1998,

[282, 105, 106, 283, 284, 285]

4.9 Geographical index The following table gives references to the contributions by country. 

Australia: [173, 202, 206, 92]





Brazil: [61, 233] Byelorussia: [35] Canada: [320, 330, 131, 143, 20, 161, 167, 254, 279]



       

   

 

 

China (incl. Hong Kong): [44, 149] Czech Republic: [82, 98, 284, 216] Denmark: [300, 127, 156, 159] Finland: [51, 91]



France: [39, 208] Germany (incl. DDR): [117, 112, 290, 306, 303, 111, 322, 139, 145, 154, 166, 29, 169, 207, 56, 57, 214, 227, 66, 231, 71, 72, 238, 239, 245, 246, 83, 85, 266, 272, 281, 283] Greece: [168]



India: [289, 292, 315, 121, 123, 10, 147, 148, 151, 171, 205, 213, 228, 243, 252, 255, 93, 96, 102, 282, 285] Italy: [304, 136, 152, 164, 183, 60, 221, 236, 244, 248, 257, 258, 260, 95] Japan: [314, 329, 118, 119, 120, 333, 334, 12, 130, 138, 141, 11, 17, 19, 21, 23, 24, 28, 184, 186, 195, 215, 219, 226, 232, 268] Kuwait: [165, 200, 286] Poland: [42, 105]

  

  





Romania: [271] Saudi Arabia: [122, 146, 176, 193, 199, 201, 274] Singapore: [106] Slovak Republic: [179] South Korea: [182, 40, 100] Spain: [34, 94] Switzerland: [223, 67] Taiwan R.o.C.: [332, 137, 163, 198] Thailand: [64] The Netherlands: [30, 38] Ukraina: [162] United Kingdom: [116, 13, 134, 16, 142, 25, 26, 27, 31, 172, 33, 177, 181, 36, 37, 41, 190, 45, 48, 50, 204, 52, 55, 211, 217, 65, 69, 74, 234, 76, 235, 78, 242, 80, 84, 247, 250, 251, 253, 86, 88, 256, 89, 90, 259, 276, 277] United States: [293, 294, 310, 295, 308, 318, 296, 297, 309, 316, 323, 324, 325, 107, 298, 299, 311, 326, 327, 108, 287, 305, 312, 317, 319, 110, 114, 115, 313, 328, 124, 125, 126, 128, 129, 132, 133, 135, 14, 15, 140, 144, 18, 150, 153, 22, 155, 157, 158, 160, 170, 32, 174, 175, 180, 187, 188, 189, 43, 191, 192, 194, 196, 197, 203, 49, 53, 210, 54, 59, 212, 62, 63, 218, 220, 222, 224, 229, 68, 70, 230, 75, 237, 240, 241, 81, 249, 87, 261, 262, 263, 264, 265, 267, 269, 270, 273, 97, 275, 99, 278, 101, 280, 103, 104] Unknown country: [58, 73]

Chapter 5

Permuted title index The words of the titles of the articles are shown in the next table arranged in alphabetical order. The most common words have been excluded. The key word is shown by a disk () in the title eld with the exception that it is omitted when appearing as the rst word of the title after shown keyword. The other abbreviation used to compress titles are shown in appendix A. accommodate Use of architecture-altering operations to dynamically adapt a three-way analog source ident. circuit to  a new source [101] adapt Use of architecture-altering operations to dynamically  a three-way analog source ident. circuit to accommodate a new source [168] adaptive An  GA for VLSI circuit partitioning [245] { An  par. GA for VLSI-layout opt. [52] { Evolving  computer syst. [327] { Macro-cell and module placement by gen.  search with bitmap-represented chromosome [115]  GA for opt. printed circuit board assembly planning [191, 220] { Perf. -driven MCM partitioning through an  GA [36] agenetic State assignment of nite state machines using  alg. [230] { SURGEN:  appr. for subcircuit extraction [233] agents Placement opt. using behavior based software  and the GA [61] { Placement opt. using behavior-based software  and the GA [42] algebraic Obtaining symbolic network functions of large circuits - an  appr. [171] algorithm-based A gen.  circuit partitioner for MCMs [205] { Synthesis of highly testable xed-polarity AND-XOR canonical networks - A gen.  appr. [167] allocation An enhanced gen. formulation for sch. , module  and binding in VLSI design [279] { Enhanced gen. solution for sch. , module  and binding in VLSI design [185] { High-level synthesis sch. and  using GAs [286] { Integrated sch. ,  and module sel. for design-space exploration in high-level synthesis [213]  and binding in data path synthesis using a GA appr. [240] Alternating strategies for sequential circuit ATPG [83] analog New gen. single-layer routing alg. for  transistor arrays [316]  component placement by GAs | part I: Partitioning [28] { Polycell placement for  LSI chip designs by GAs and tabu search [101] { Use of architecture-altering operations to dynamically adapt a three-way  source ident. circuit to accommodate a new source [27] analogue Automatic  network synthesis using GAs [90] { Evol. design of  electronic circuits; current status [86] { GAs design of electronic  circuits including parasitic eects [317]  placement by formulation of macrocomponents and gen. partitioning [38] analogue circuit DARWIN:  synthesis based on GAs

[101]

analogue circuits GA design of electronic  including parasitic eects [64] analysis Atomatic circuit simpli cation for meaningful symbolic  using the GA [44] { Circuit worst-case tolerance  via solutions of interval linear equations [95] { Gen. opt. of interval mathematics-based sensitivity  of switching converters [188] analyzing Ecient alg. for  and synthesizing faulttolerant datapaths [46] AND/EXOR A GA for 2-level  minimization [69] AND-EXOR Symbolic method for simplifying  Rep. of Boolean functions using a binary-decision technique and a GA [55] AND-EXOR networks Restricted evaluation GAs with tabu search for opt. Boolean functions as multi-level  [205] AND-XOR Synthesis of highly testable xed-polarity  canonical networks - A GA-based appr. [117] Anwendbarkeit Untersuchung uber die  der ES in der Nachrichtentechnik [91] APLACTM Circuit Simulation and Design Tool, User's Manual [192] application A gen. appr. to test  time reduction for full scan circuits [17] { A study on  of GA to automatic placement of parts on printed circuit boards [268] { An evol. opt. based on the immune syst. and its  to the VLSI oorplan design problem [111] Application ES in der Halbleitertechnik fur die Charakterisierung von MOS-bauelementen  of evol. strategy in semiconductor modeling for the characterization of MOSdevices] [123] application GA for embedding a complete graph in a hypercube with a VLSI  [14] { GAs for thermosciences research:  to the optimized cooling of electronic components [82]  of a GA for evaluation of a quenching test by an inverse task with an unknown time constant of a sensor [107]  of gen. based alg. to opt. capacitor placement [162]  of mutants as operators of GAs for optimising of VLSI and PCB elements placement on the basis of scanning area method [22]  of simple GA to sequential circuit test generation [109]  of the evol. strategy to optimize multistep eld plates for high voltage planar pn-junctions [215] { Opt. of neighborhood size for par. local search and its  to test generation of combinational circuits [156] { SAGA: a uni cation of the GA with simulated annealing and its  to macro-cell placement [89]

23

[181] applications A par. gen. VLSI architecture for comb. real-time  - Disc sch. [292] { GA for node partitioning problem and  in VLSI design [40]  of evol. computations at LG Electronics [309] { Opt. by simulated evol. with  to standard cell placement [212] applied GAs  to the physical design of VLSI circuits: A survey [99] { Syst. based intelligent cntr.  to electronic test generation and diagnostics using FuzzyART and GAs [170] { The GA  to gate sizing [287] Applying GAs to the state assignment problem: a case study [330]  simulated evol. to high level synthesis [100] architecture A gen. -alg. -based high-level synthesis for partitioned bus  [181] { A par. gen. VLSI  for comb. real-time appl. - Disc sch. [79] architecture-altering Use of automatically de ned functions and  operations in automated circuit synthesis using gen. prog. [101] { Use of  operations to dynamically adapt a three-way analog source ident. circuit to accommodate a new source [221] area A cellular GA for the oorplan  opt. problem on a SIMD architecture [162] { Appl. of mutants as operators of GAs for optimising of VLSI and PCB elements placement on the basis of scanning  method [153] { Floorplan  opt. using GAs [244] { GALLO: a GA for oorplan  opt. [197] { Perf. and  opt. of VLSI syst. using GAs [83] arrays New gen. single-layer routing alg. for analog transistor  [318] ASIC An evol. -based appr. to partitioning  syst. [303] assembly Chip  in the PLAYOUT VLSI design syst. [106] { PCB  planning using GAs [114] { Planning of component placement/insertion sequence and feeder setup in PCB  using GA [54] assembly lines Balancing SMD  with GAs [115] assembly planning Adaptive GA for opt. printed circuit board  [63] assembly system A GA for determining facility design and con guration of single-stage exible electronic  [287] assignment Applying GAs to the state  problem: a case study [160] { Designing GAs for the state  problem [282] { GA based appr. for integrated state  and ip op sel. in nite stateBLmachine synthesis [158] { GAs for partitioning, placement, and layer  for multichip modules [198] { Gen. -based rotation  in marco cell layout [155] { MCM layer  using gen. search [135] { State  for low-power FSM synthesis using gen. local search [36] { State  of nite state machines using aGA [129] associative memories Modular scheme for designing special purpose  and beyond [64] Atomatic circuit simpli cation for meaningful symbolic analysis using the GA [208] ATPG A diagnostic  for delay faults based on GAs [240] { Alternating strategies for sequential circuit  [125] { Iterative [simulation-based gen. + deterministic techniques] = complete  [190] { Syst. design for test using a gen. based hierarchical  syst. [236] ATPGs Advanced techniques for GA-based sequential  [258] { Comparing topological, symbolic and GA-based  an experimental appr. [257, 260] { Partial scan ip op sel. for simulation-based sequential  [119] attempt An  to solve channel routing using GA [211] automate Using GAs to  syst. impl. in a novel threedimensional packaging technology [21] automated Evol.  hardware design syst. with HDL [103]  synthesis of computational circuits using gen. prog. [59]  WYSIWYG design of both the topology and component values of electrical circuits using gen. prog. [79] { Use of automatically de ned functions and architecture-altering operations in  circuit synthesis using gen. prog.

[17] automatic A study on appl. of GA to  placement of parts on printed circuit boards [152] { An  test pattern generator for large sequential circuits based on GAs [136] { GATTO: an intelligent tool for  test pattern generation for digital circuits [262] { Next generation test generator (NGTG) interface to  test equipment [27]  analogue network synthesis using GAs [24]  hardware design with an evol. process [210]  test generation using gen. -engineered distinguishing sequences [224]  test vector cultivation for sequential VLSI circuits using GAs [285]  test pattern generation for sequential circuits using GAs [248] { Gatto: a GA for  test pattern generation for large synchronous sequential circuits [79] automatically Use of  de ned functions and architecture-altering operations in automated circuit synthesis using gen. prog. [227] automation A GA for VLSI physical design  [225, 193] { VLSI Physical Design  Theory and Practice [29] balance GA: A new appr. to energy  equations [54] Balancing SMD assembly lines with GAs [162] basis Appl. of mutants as operators of GAs for optimising of VLSI and PCB elements placement on the  of scanning area method [66] batteries Gen. opt. of a fuzzy syst. for charging  [84] BDDS Improved variable ordering of  with novel GA [140] beam Gen.  search for gate matrix layout [328] beam search Gen.  for gate matrix layout [58] beats Hill climbing  gen. search on a Boolean circuit synthesis problem of Koza's [233] behavior Placement opt. using  based software agents and the GA [61] behavior-based Placement opt. using  software agents and the GA [12] behaviors Development and evol. of hardware  [322] Beitrage Massiv par. e genetische Algorithmen,  zum Tag der Informatik Erlangen 1993 [226] binary Evol. of  decision diagrams for digital circuit design using gen. prog. [45] { Minimisation of multioutput Reed-Muller  decision diagrams using hybrid GA. [25] { Using GAs for the variable ordering of Reed-Muller  decision diagrams [69] binary-decision Symbolic method for simplifying AND-EXOR Rep. of Boolean functions using a  technique and a GA [213] binding Allocation and  in data path synthesis using a GA appr. [167] { An enhanced gen. formulation for sch. , module allocation, and  in VLSI design [279] { Enhanced gen. solution for sch. , module allocation, and  in VLSI design [143] BIST Selecting prog. mable space compactors for  using GAs [272] bist-architecture On opt.  by using OBDD-based appr. and GAs [327] bitmap-represented Macro-cell and module placement by gen. adaptive search with  chromosome [58] Boolean Hill climbing beats gen. search on a  circuit synthesis problem of Koza's [187] { Improved technology mapping using a new appr. to  matching [94] Boolean networks decomposition using GAs [55] Boolean functions Restricted evaluation GAs with tabu search for opt.  as multi-level AND-EXOR networks [69] { Symbolic method for simplifying AND-EXOR Rep. of  using a binary-decision technique and a GA [13] { Using a GA for opt. zed polarity Reed-Muller expansions of  [229] bridging Gen. -alg. -based test generation for current testing of  faults in CMOS VLSI circuits [180] { Test generation for current testing of  faults in CMOS VLSI circuits [232] Built-in multiple weighted random testing based on GAs [100] bus A gen. -alg. -based high-level synthesis for partitioned  architecture

[283] CAD Evol. Alg. for VLSI  [57] calculation Evol. alg. for the  of electron distributions in Si-MOSFETs [80] canonical Non-exhaustive search methods and their use in the minimization of Reed-Muller  expansions [205] { Synthesis of highly testable xed-polarity AND-XOR  networks - A GA-based appr. [107] capacitor Appl. of gen. based alg. to opt.  placement [300] cell A GA for macro  placement [184]  placement by GA [309] { Opt. by simulated evol. with appl. to standard  placement [310] { Esp: A new standard  placement package using simulated evol. [325] { Gasp - a GA for standard  placement [324] { Standard  Placement and the GA [291] { Standard  Routing Opt. Using A GA [326] { VLSI  placement techniques [312, 313] { Wolverines: standard  placement on a network of workstations [259] cell-based Structral  VLSI circuit design using a GA [253] { Structural synthesis of  VLSI circuits using a multiobjective geentic alg. [247] { Structural synthesis of  VLSI circuits using a multiobjective GA [234] { Structural  VLSI circuit design using a GA [221] cellular A  GA for the oorplan area opt. problem on a SIMD architecture [11] channel Gen.  router [182] { Genrouter: a GA for  routing-problems [138] { Modi ed gen.  router [269]  and switchbox routing with minimized crosstalk. A par. GA appr. [151] channel router A par. EP-based  [203, 261] channel routing A GA for VLSI  in the presence of cyclic vertical constraints [157] { A GA for  in VLSI circuits [10] { A GA for  using inter-cluster mutation [329] { An appr. to  using GA [119] { An attempt to solve  using GA [174] { An extended EP alg. for VLSI  [219] { Constrained opt. with GAs:  case [289] { Extended distr. GA for  [238] { Hybrid GA for the  problem [288] { Par. GA for  [118] { Restrictive  with evol. prog. [120] { Restrictive  with hybrid GAs [314] channel routing problem A GA for  [209] { A hybrid GA for the  [131] { New GA for the  [111] characterization ES in der Halbleitertechnik fur die Charakterisierung von MOS-bauelementen [Application of evol. strategy in semiconductor modeling for the  of MOSdevices] [111] Charakterisierung ES in der Halbleitertechnik fur die  von MOS-bauelementen [Application of evol. strategy in semiconductor modeling for the characterization of MOSdevices] [66] charging Gen. opt. of a fuzzy syst. for  batteries [303] Chip assembly in the PLAYOUT VLSI design syst. [112] Chip-Assembly Strategien bei der Layout-Synthese nach Floorplan-Vorgaben [327] chromosome Macro-cell and module placement by gen. adaptive search with bitmap-represented  [271] chromosomes Design elements of EHW using GA with local improvement of  [171] circuit A GA-based  partitioner for MCMs [240] { Alternating strategies for sequential  ATPG [168] { An adaptive GA for VLSI  partitioning [91] { APLACTM  Simulation and Design Tool, User's Manual [22] { Appl. of simple GA to sequential  test generation [64] { Atomatic  simpli cation for meaningful symbolic analysis using the GA [105] { Evol. al searching for  structures [290] { GAs and VLSI  design [51] { Gen. opt. in  simulation [124]  synthesis through gen. prog. [44]  worst-case tolerance analysis via solutions of interval linear equations [15] { Sequential  test generation in a GA framework

[161] { Towards opt.  layout using advanced search techniques [101] { Use of architecture-altering operations to dynamically adapt a three-way analog source ident.  to accommodate a new source [79] { Use of automatically de ned functions and architecture-altering operations in automated  synthesis using gen. prog. [126] { VLSI  synthesis using a par. GA [49] circuit partitioning A hybrid multilevel/gen. appr. for  [58] circuit synthesis problem Hill climbing beats gen. search on a Boolean  of Koza's [218] circuits A framework for estimating maximum powerdissipation in CMOS combinational  using GAs [192] { A gen. appr. to test appl. time reduction for full scan  [152] { An automatic test pattern generator for large sequential  based on GAs [103] { Automated synthesis of computational  using gen. prog. [59] { Automated WYSIWYG design of both the topology and component values of electrical  using gen. prog. [104] { Design of a high-gain operational ampli er and other  by means of gen. prog. [71] { Design of multivalued  using GAs [231, 246] { Evol. synthesis of current-mode CMOS 4-valued  [134] { Generating test patterns for VLSI  using a GA [128] { GA based design opt. of CMOS VLSI  [284] { GA for partitioning  [86] { GAs design of electronic analogue  including parasitic eects [320] { GAs for the opt. of integrated  synthesis [50] { Gen. synthesis techniques for low-power digital signal processing  [256] { Gen. synthesis techniques for low-power digital signal processing  [42] { Obtaining symbolic network functions of large  - an algebraic appr. [215] { Opt. of neighborhood size for par. local search and its appl. to test generation of combinational  [60] { Small-signal modelling for microwave FET linear  based on a GA [275] { Text generation test generator (NGTG) for digital  [251] { Transitional gate delay detection for combinational  using a GA [186] cluster Design of a compact  structure by using GAs [218] CMOS A framework for estimating maximum powerdissipation in  combinational circuits using GAs [30] { DARWIN:  opamp synthesis by means of a GA [231, 246] { Evol. synthesis of current-mode  4-valued circuits [128] { GA based design opt. of  VLSI circuits [229] { Gen. -alg. -based test generation for current testing of bridging faults in  VLSI circuits [223] { Stochastic methods for transistor size opt. of  VLSI circuits [180] { Test generation for current testing of bridging faults in  VLSI circuits [321] CMOS-array Neural networks and GAs as prog. paradigm for a new  computer [183] codesign Soft computing appr. to hardware software  [133] coding Pioneer: A new tool for  of multi-level nite state machines based on evol. prog. [218] combinational A framework for estimating maximum powerdissipation in CMOS  circuits using GAs [276] { A GA for multiple fault model test generation for  VLSI circuits [31]  and sequential logic opt. using GAs [215] { Opt. of neighborhood size for par. local search and its appl. to test generation of  circuits [277] { The derivation of minimal test sets for  logic cuircuits using GAs [251] { Transitional gate delay detection for  circuits using a GA [181] combinatorial A par. gen. VLSI architecture for  real-time appl. - Disc sch. [68] combinatorial circuits Fast alg. for computing Iddq tests for  [175] Combining deterministic and gen. appr. for sequential circuit test generation [186] compact Design of a  cluster structure by using GAs

[297] Compacting randomly generated test sets [298] { Gate - A GA for  randomly generated test sets [267] compaction On the  of test sets produced by gen. opt. [258] Comparing topological, symbolic and GA-based ATPGs: an experimental appr. [32] comparison A  of EP and GAs for electronic part placement [87] competitive Four problems for which a computer prog. evolved by gen. prog. is  with human perf. [123] complete GA for embedding a  graph in a hypercube with a VLSI appl. [125] { Iterative [simulation-based gen. + deterministic techniques] =  ATPG [316] component Analog  placement by GAs | part I: Partitioning [59] { Automated WYSIWYG design of both the topology and  values of electrical circuits using gen. prog. [70]  sel. using hybrid opt. alg. [114] { Planning of  placement/insertion sequence and feeder setup in PCB assembly using GA [14] components GAs for thermosciences research: Appl. to the optimized cooling of electronic  [214] { Prototyping of VLSI  from a formal speci cation [103] computational Automated synthesis of  circuits using gen. prog. [40] computations Appl. of evol.  at LG Electronics [68] computing Fast alg. for  Iddq tests for comb. circuits [63] con guration A GA for determining facility design and  of single-stage exible electronic assembly syst. [82] constant Appl. of a GA for evaluation of a quenching test by an inverse task with an unknown time  of a sensor [219] Constrained opt. with GAs: channel routing case [203, 261] constraints A GA for VLSI channel routing in the presence of cyclic vertical  [77] construction A GA for the  of small and highly testable OKFDD circuits [92] continuous Digital redesign of  syst. with improved suitability using GAs [222] control GA for low variance  in semiconductor device manufacturing: some early results [73] { Soft computing in power electronics and motion  [99] { Syst. based intelligent  appl. to electronic test generation and diagnostics using FuzzyART and GAs [95] converters Gen. opt. of interval mathematics-based sensitivity analysis of switching  [95] { Gen. opt. of interval mathematics-based sensitivity analysis of switching  [14] cooling GAs for thermosciences research: Appl. to the optimized  of electronic components [319] CRIS A test cultivation prog. for sequential VLSI circuits [269] crosstalk Channel and switchbox routing with minimized  A par. GA appr. [277] cuircuits The derivation of minimal test sets for combinational logic  using GAs [224] cultivation Automatic test vector  for sequential VLSI circuits using GAs [319] { CRIS: A test  prog. for sequential VLSI circuits [278] current Estimation of maximum power and instantaneous  using a GA [90] { Evol. design of analogue electronic circuits;  status [229] { Gen. -alg. -based test generation for  testing of bridging faults in CMOS VLSI circuits [180] { Test generation for  testing of bridging faults in CMOS VLSI circuits [231, 246] current-mode Evol. synthesis of  CMOS 4-valued circuits [203, 261] cyclic A GA for VLSI channel routing in the presence of  vertical constraints [333] Darwin Evolving hardware with gen. learning: A rst step towards building a  machine [38] DARWIN analogue circuit synthesis based on GAs [30]  CMOS opamp synthesis by means of a GA [39] databases Run time recon guration of FPGA for scanning genomic  [165] Datapath synthesis using a problem-space GA [188] datapaths Ecient alg. for analyzing and synthesizing fault-tolerant  [255] { Synthesis of testable pipelined  using gen. search [75] decibel Evol. of a 60  op amp using gen. prog.

[45] decision Minimisation of multioutput Reed-Muller binary  diagrams using hybrid GA. [41] { Ternary  diagram opt. of Reed-Muller logic functions using a GA for variable and simpli cation rule ordering [25] { Using GAs for the variable ordering of Reed-Muller binary  diagrams [226] decision diagrams Evol. of binary  for digital circuit design using gen. prog. [122] decoder GAP: a GA appr. to optimize two-bit  PLAs [94] decomposition Boolean networks  using GAs [79] de ned Use of automatically  functions and architecture-altering operations in automated circuit synthesis using gen. prog. [208] delay A diagnostic ATPG for  faults based on GAs [251] { Transitional gate  detection for combinational circuits using a GA [88] { Transitional  fault test generation using a GA [277] derivation The  of minimal test sets for combinational logic cuircuits using GAs [63] design A GA for determining facility  and con guration of single-stage exible electronic assembly syst. [227] { A GA for VLSI physical  automation [178] { A par. GA for multi-objective microprocessor  [264] { A perf. -driven IC/MCM placement alg. featuring explicit  space exploration [167] { An enhanced gen. formulation for sch. , module allocation, and binding in VLSI  [268] { An evol. opt. based on the immune syst. and its appl. to the VLSI oorplan  problem [91] { APLACTM Circuit Simulation and  Tool, User's Manual [59] { Automated WYSIWYG  of both the topology and component values of electrical circuits using gen. prog. [24] { Automatic hardware  with an evol. process [303] { Chip assembly in the PLAYOUT VLSI  syst. [299] { Distr. GAs for the oorplan  problem [279] { Enhanced gen. solution for sch. , module allocation, and binding in VLSI  [226] { Evol. of binary decision diagrams for digital circuit  using gen. prog. [21] { Evol. automated hardware  syst. with HDL [90] { Evol.  of analogue electronic circuits; current status [295] { Floorplan  using distr. GAs [128] { GA based  opt. of CMOS VLSI circuits [292] { GA for node partitioning problem and appl. in VLSI  [18] { GA techniques for 3-valued transistor  [89] { GA  of electronic analogue circuits including parasitic eects [113] { GA  of neural net based electronic nose [290] { GAs and VLSI circuit  [212] { GAs appl. to the physical  of VLSI circuits: A survey [252] { GAs for scan path  [86] { GAs  of electronic analogue circuits including parasitic eects [177] { Gen.  of VLSI-layouts [237] { MCM/IC timing-driven placement alg. featuring explicit  space exploration [35] { Neural technologies and GAs in modern logic  [271]  elements of EHW using GA with local improvement of chromosomes [186]  of a compact cluster structure by using GAs [104]  of a high-gain operational ampli er and other circuits by means of gen. prog. [16]  of HDL prog. for digital-syst. using GAs [71]  of multivalued circuits using GAs [249]  space exploration using the GA [259] { Structral cell-based VLSI circuit  using a GA [234] { Structural cell-based VLSI circuit  using a GA [190] { Syst.  for test using a gen. based hierarchical ATPG syst. [225] { VLSI Physical  Automation, Theory and Practice [193] { VLSI Physical  Automaton: Theory and Practice [56] design process GA and simulator speed up electronic  [129] designing Modular scheme for  special purpose associative memories and beyond [65]  digital syst. using GAs [160]  GAs for the state assignment problem [28] designs Polycell placement for analog LSI chip  by GAs and tabu search

[286] design-space Integrated sch. , allocation and module sel. for  exploration in high-level synthesis [241] detailed A par. GA for two  routing problems [301] { A  router based on simulated evol. [251] detection Transitional gate delay  for combinational circuits using a GA [63] determining A GA for  facility design and con guration of single-stage exible electronic assembly syst. [175] deterministic Combining  and gen. appr. for sequential circuit test generation [125] { Iterative [simulation-based gen. +  techniques] = complete ATPG [19] development HDL-prog.  modeled upon embryonic  [12]  and evol. of hardware behaviors [222] device GA for low variance cntr. in semiconductor  manufacturing: some early results [208] diagnostic A  ATPG for delay faults based on GAs [99] diagnostics Syst. based intelligent cntr. appl. to electronic test generation and  using FuzzyART and GAs [41] diagram Ternary decision  opt. of Reed-Muller logic functions using a GA for variable and simpli cation rule ordering [45] diagrams Minimisation of multioutput Reed-Muller binary decision  using hybrid GA. [25] { Using GAs for the variable ordering of Reed-Muller binary decision  [50] digital Gen. synthesis techniques for low-power  signal processing circuits [256] { Gen. synthesis techniques for low-power  signal processing circuits [92]  redesign of continuous syst. with improved suitability using GAs [275] { Text generation test generator (NGTG) for  circuits [226] digital circuit Evol. of binary decision diagrams for  design using gen. prog. [93] digital circuits A GA appr. to high-level synthesis of  [136] { GATTO: an intelligent tool for automatic test pattern generation for  [65] digital systems Designing  using GAs [16] digital-systems Design of HDL prog. for  using GAs [181] Disc scheduling A par. gen. VLSI architecture for comb. real-time appl. -  [210] distinguishing Automatic test generation using gen. engineered  sequences [311] distributed A  GA for standard cell placement on a network of workstations [289] { Extended  GA for channel routing [295] { Floorplan design using  GAs [299]  GAs for the oorplan design problem [57] distributions Evol. alg. for the calculation of electron  in Si-MOSFETs [199] driven Perf.  standard-cell placement using the GA [176] { Timing  GA for standard-cell placement [235] DSP Gen. framework for the high level opt. of low power VLSI  syst. [204] DSP systems A gen. framework for the high-level opt. of low power VLSI  [172, 217] dynamic Hierarchical test pattern generation using a GA with a  global reference table [101] dynamically Use of architecture-altering operations to  adapt a three-way analog source ident. circuit to accommodate a new source [222] early GA for low variance cntr. in semiconductor device manufacturing: some  results [188] Ecient alg. for analyzing and synthesizing faulttolerant datapaths [271] EHW Design elements of  using GA with local improvement of chromosomes [334] electric circuitry Evolvable hardware { gen. based generation of  at gate and hardware description language (HDL) levels [59] electrical Automated WYSIWYG design of both the topology and component values of  circuits using gen. prog. [57] electron Evol. alg. for the calculation of  distributions in Si-MOSFETs [32] electronic A comparison of EP and GAs for  part placement [63] { A GA for determining facility design and con guration of single-stage exible  assembly syst. [33] { A neural network impl. for an  nose

[56] { GA and simulator speed up  design process [113] { GA design of neural net based  nose [89] { GA design of  analogue circuits including parasitic effects [86] { GAs design of  analogue circuits including parasitic eects [14] { GAs for thermosciences research: Appl. to the optimized cooling of  components [99] { Syst. based intelligent cntr. appl. to  test generation and diagnostics using FuzzyART and GAs [90] electronic circuits; Evol. design of analogue  current status [72] electronic-circuits Syst. for opt. of  using GA [62] electronics Overview of evol. syst. for industrial  [73] { Soft computing in power  and motion cntr. [162] elements Appl. of mutants as operators of GAs for optimising of VLSI and PCB  placement on the basis of scanning area method [271] { Design  of EHW using GA with local improvement of chromosomes [123] embedding GA for  a complete graph in a hypercube with a VLSI appl. [19] embryonic HDL-prog. development modeled upon  development [132] empirical Hybrid GAs with hyperplane synthesis: A theoretical and  study [29] energy GA: A new appr. to  balance equations [167] enhanced An  gen. formulation for sch. , module allocation, and binding in VLSI design [279]  gen. solution for sch. , module allocation, and binding in VLSI design [174] EP An extended  alg. for VLSI channel routing [44] equations Circuit worst-case tolerance analysis via solutions of interval linear  [29] { GA: A new appr. to energy balance  [296] equilibria GAs and punctuated  in VLSI [262] equipment Next generation test generator (NGTG) interface to automatic test  [322] Erlangen Massiv par. e genetische Algorithmen, Beitrage zum Tag der Informatik  1993 [310] Esp A new standard cell placement package using simulated evol. [308]  Placement by simulated evol. [218] estimating A framework for  maximum powerdissipation in CMOS combinational circuits using GAs [278] Estimation of maximum power and instantaneous current using a GA [82] evaluation Appl. of a GA for  of a quenching test by an inverse task with an unknown time constant of a sensor [164] { Impl. and  of GAs for syst. partitioning [55] { Restricted  GAs with tabu search for opt. Boolean functions as multi-level AND-EXOR networks [301] evolution A detailed router based on simulated  [330] { Applying simulated  to high level synthesis [12] { Development and  of hardware behaviors [23] { Hardware  { an HDL appr. [75]  of a 60 decibel op amp using gen. prog. [226]  of binary decision diagrams for digital circuit design using gen. prog. [309] { Opt. by simulated  with appl. to standard cell placement [332] { Perf. -driven global routing based on simulated  [133] { Pioneer: A new tool for coding of multi-level nite state machines based on  prog. [118] { Restrictive channel routing with  prog. [310] { Esp: A new standard cell placement package using simulated  [308] { Esp: Placement by simulated  [74] { Silicon  [302] { SILK: Simulated  router [331] { Solving gate-matrix layout problems by simulated  [109] evolution strategy Appl. of the  to optimize multistep eld plates for high voltage planar pn-junctions [111] { ES in der Halbleitertechnik fur die Charakterisierung von MOS-bauelementen [Application of  in semiconductor modeling for the characterization of MOS-devices] [105] Evolutional searching for circuit structures [32] evolutionary A comparison of  prog. and GAs for electronic part placement [151] { A par.  prog. -based channel router [20] { An  alg. for the routing of multi-chip modules

[67] { An  appr. to syst. -level synthesis [268] { An  opt. based on the immune syst. and its appl. to the VLSI oorplan design problem [40] { Appl. of  computations at LG Electronics [24] { Automatic hardware design with an  process [78, 250] { Experiences of using  techniques in logic minimisation [207] { Learning heuristics for OBDD minimization by  alg. [57]  alg. for the calculation of electron distributions in Si-MOSFETs [283]  Alg. for VLSI CAD [21]  automated hardware design syst. with HDL [90]  design of analogue electronic circuits; current status [231, 246]  synthesis of current-mode CMOS 4-valued circuits [48]  techniques for fault tolerance [62] { Overview of  syst. for industrial electronics [318] evolution-based An  appr. to partitioning ASIC syst. [111] Evolutionsstrategie in der Halbleitertechnik fur die Charakterisierung von MOS-bauelementen [Application of evol. strategy in semiconductor modeling for the characterization of MOS-devices] [117] Evolutionsstrategie Untersuchung uber die Anwendbarkeit der  in der Nachrichtentechnik [334] Evolvable hardware { gen. based generation of electric circuitry at gate and hardware description language (HDL) levels [87] evolved Four problems for which a computer prog.  by gen. prog. is competitive with human perf. [52] Evolving adaptive computer syst. [333]  hardware with gen. learning: A rst step towards building a Darwin machine [80] expansions Non-exhaustive search methods and their use in the minimization of Reed-Muller canonical  [13] { Using a GA for opt. zed polarity Reed-Muller  of Boolean functions [78, 250] Experiences of using evol. techniques in logic minimisation [258] experimental Comparing topological, symbolic and GA-based ATPGs: an  appr. [98]  study par. GA for placement opt. [239] experts Hierarchical strategy of model partitioning for VLSI-design using an improve mixture of  appr. [264] explicit A perf. -driven IC/MCM placement alg. featuring  design space exploration [237] { MCM/IC timing-driven placement alg. featuring  design space exploration [264] exploration A perf. -driven IC/MCM placement alg. featuring explicit design space  [249] { Design space  using the GA [286] { Integrated sch. , allocation and module sel. for designspace  in high-level synthesis [237] { MCM/IC timing-driven placement alg. featuring explicit design space  [166] expressions A GA for minimization of xed polarity Reed-Muller  [108] extracting A modi ed GA for  thermal pro les from infrared image data [230] extraction SURGEN: agen. appr. for subcircuit  [63] facility A GA for determining  design and con guration of single-stage exible electronic assembly syst. [68] Fast alg. for computing Iddq tests for comb. circuits [150]  and stable hybrid GA for the ratio-cut partitioning problem on hypergraphs [276] fault A GA for multiple  model test generation for combinational VLSI circuits [266] { A GA for sequential circuit test generation based on symbolic  simulation [48] { Evol. techniques for  tolerance [88] { Transitional delay  test generation using a GA [208] faults A diagnostic ATPG for delay  based on GAs [229] { Gen. -alg. -based test generation for current testing of bridging  in CMOS VLSI circuits [180] { Test generation for current testing of bridging  in CMOS VLSI circuits [188] fault-tolerant Ecient alg. for analyzing and synthesizing  datapaths [305] feasibility A  study of gen. placement [264] featuring A perf. -driven IC/MCM placement alg.  explicit design space exploration [237] { MCM/IC timing-driven placement alg.  explicit design space exploration

[114] feeder Planning of component placement/insertion sequence and  setup in PCB assembly using GA [60] FET Small-signal modelling for microwave  linear circuits based on a GA [109] eld Appl. of the evol. strategy to optimize multistep  plates for high voltage planar pn-junctions [81] lms Recipe synthesis for PECVD SiO2  using neural networks and GAs [133] nite Pioneer: A new tool for coding of multi-level  state machines based on evol. prog. [26] Finite Element Analysis GA Opt. of Load Cell Geometry by  [37] nite element analysis Load cell shape opt. using GAs and  [36] nite state machines State assignment of  using aGA [282] nite stateBLmachine GA based appr. for integrated state assignment and ip op sel. in  synthesis [166] xed A GA for minimization of  polarity Reed-Muller expressions [145] { OFDD based minimization of  polarity Reed-Muller expressions using hybrid GAs [205] xed-polarity Synthesis of highly testable  ANDXOR canonical networks - A GA-based appr. [13] zed Using a GA for opt.  polarity Reed-Muller expansions of Boolean functions [63] exible A GA for determining facility design and con guration of single-stage  electronic assembly syst. [257, 260] ip op Partial scan  sel. for simulation-based sequential ATPGs [282] ip op GA based appr. for integrated state assignment and  sel. in nite stateBLmachine synthesis [221] oorplan A cellular GA for the  area opt. problem on a SIMD architecture [268] { An evol. opt. based on the immune syst. and its appl. to the VLSI  design problem [299] { Distr. GAs for the  design problem [244] { GALLO: a GA for  area opt. [153]  area opt. using GAs [295]  design using distr. GAs [195] oorplan design A VLSI  based on gen. immune recruitment mechanism [201] oorplanner Timing in uenced general-cell gen.  [274] { Timing-in uenced general-cell gen.  [112] Floorplan-Vorgaben Chip-Assembly Strategien bei der Layout-Synthese nach  [214] formal Prototyping of VLSI components from a  speci cation [167] formulation An enhanced gen.  for sch. , module allocation, and binding in VLSI design [317] { Analogue placement by  of macrocomponents and gen. partitioning [39] FPGA Run time recon guration of  for scanning genomic databases [142] FPGAs Opt. techniques based on the use of GAs (GAs) for logic impl. on  [163] FPGA's TRACER-fpga: a router for RAM-based  [263] framework A GA  for test generation [204] { A gen.  for the high-level opt. of low power VLSI DSP syst. [218] { A  for estimating maximum powerdissipation in CMOS combinational circuits using GAs [235] { Gen.  for the high level opt. of low power VLSI DSP syst. [15] { Sequential circuit test generation in a GA  [135] FSM State assignment for low-power  synthesis using gen. local search [42] functions Obtaining symbolic network  of large circuits - an algebraic appr. [79] { Use of automatically de ned  and architecturealtering operations in automated circuit synthesis using gen. prog. [66] fuzzy system Gen. opt. of a  for charging batteries [99] FuzzyART Syst. based intelligent cntr. appl. to electronic test generation and diagnostics using  and GAs [236] GA-based Advanced techniques for  sequential ATPGs [258] { Comparing topological, symbolic and  ATPGs: an experimental appr. [244] GALLO a GA for oorplan area opt. [122] GAP a GA appr. to optimize two-bit decoder PLAs

[254] GASBOR a GA appr. for solving the switchbox routing problem [325] Gasp - a GA for standard cell placement [334] gate Evolvable hardware { gen. based generation of electric circuitry at  and hardware description language (HDL) levels [140] { Gen. beam search for  matrix layout [170] { The GA appl. to  sizing [251] { Transitional  delay detection for combinational circuits using a GA [328] gate matrix Gen. beam search for  layout [121] { On the synthesis of  layout [298] Gate - A GA for compacting randomly generated test sets [331] gate-matrix Solving  layout problems by simulated evol. [136] GATTO an intelligent tool for automatic test pattern generation for digital circuits [248] Gatto a GA for automatic test pattern generation for large synchronous sequential circuits [253] geentic Structural synthesis of cell-based VLSI circuits using a multi-objective  alg. [53] Geep - a low-power GA layout syst. [265] Geep A low power GA layout syst. [201] general-cell Timing in uenced  gen. oorplanner [274] { Timing-in uenced  gen. oorplanner [297] generated Compacting randomly  test sets [298] { Gate - A GA for compacting randomly  test sets [134] Generating test patterns for VLSI circuits using a GA [242]  test patterns for VLSI circuits using a GA [228] { On  opt. signal probabilities for random tests: a gen. appr. [276] generation A GA for multiple fault model test  for combinational VLSI circuits [263] { A GA framework for test  [315] { A simulation-based test  scheme using GAs [22] { Appl. of simple GA to sequential circuit test  [210] { Automatic test  using gen. -engineered distinguishing sequences [285] { Automatic test pattern  for sequential circuits using GAs [175] { Combining deterministic and gen. appr. for sequential circuit test  [334] { Evolvable hardware { gen. based  of electric circuitry at gate and hardware description language (HDL) levels [136] { GATTO: an intelligent tool for automatic test pattern  for digital circuits [229] { Gen. -alg. -based test  for current testing of bridging faults in CMOS VLSI circuits [172, 217] { Hierarchical test pattern  using a GA with a dynamic global reference table [43] { LOCSTEP: A logic simulation based test  procedure [262] { Next  test generator (NGTG) interface to automatic test equipment [273] { On improving gen. opt. based test  [215] { Opt. of neighborhood size for par. local search and its appl. to test  of combinational circuits [179] { RTL level test  using GA and simulated annealing [248] { Gatto: a GA for automatic test pattern  for large synchronous sequential circuits [15] { Sequential circuit test  in a GA framework [99] { Syst. based intelligent cntr. appl. to electronic test  and diagnostics using FuzzyART and GAs [180] { Test  for current testing of bridging faults in CMOS VLSI circuits [275] { Text  test generator (NGTG) for digital circuits [88] { Transitional delay fault test  using a GA [152] generator An automatic test pattern  for large sequential circuits based on GAs [262] { Next generation test  (NGTG) interface to automatic test equipment [275] { Text generation test  (NGTG) for digital circuits [100] genetic-algorithm-based A  high-level synthesis for partitioned bus architecture [229]  test generation for current testing of bridging faults in CMOS VLSI circuits [190] genetically Syst. design for test using a  based hierarchical ATPG syst. [210] genetically-engineered Automatic test generation using  distinguishing sequences

[198] Genetic-based rotation assignment in marco cell layout [125] genetics Iterative [simulation-based  + deterministic techniques] = complete ATPG [96]  based redundancy opt. [149] genetic-type A new variable step-size alg. using  search [39] genomic Run time recon guration of FPGA for scanning  databases [182] Genrouter a GA for channel routing-problems [26] Geometry GA Opt. of Load Cell  by Finite Element Analysis [306] global A GA for  improvement of macrocell layouts [159] { A macro-cell  router based on two GAs [172, 217] { Hierarchical test pattern generation using a GA with a dynamic  reference table [332] { Perf. -driven  routing based on simulated evol. [123] graph GA for embedding a complete  in a hypercube with a VLSI appl. [146] graphs Gen. sch. of task  [111] Halbleitertechnik ES in der  fur die Charakterisierung von MOS-bauelementen [Application of evol. strategy in semiconductor modeling for the characterization of MOS-devices] [24] hardware Automatic  design with an evol. process [12] { Development and evol. of  behaviors [21] { Evol. automated  design syst. with HDL [334] { Evolvable  { gen. based generation of electric circuitry at gate and hardware description language (HDL) levels [333] { Evolving  with gen. learning: A rst step towards building a Darwin machine [23]  evol. { an HDL appr. [183] { Soft computing appr. to  software codesign [334] hardware description language Evolvable hardware { gen. based generation of electric circuitry at gate and  (HDL) levels [16] HDL Design of  prog. for digital-syst. using GAs [21] { Evol. automated hardware design syst. with  [334] { Evolvable hardware { gen. based generation of electric circuitry at gate and hardware description language  levels [23] { Hardware evol. { an  appr. [19] HDL-program development modeled upon embryonic development [207] heuristics Learning  for OBDD minimization by evol. alg. [239] Hierarchical strategy of model partitioning for VLSIdesign using an improve mixture of experts appr. [172, 217]  test pattern generation using a GA with a dynamic global reference table [190] { Syst. design for test using a gen. based  ATPG syst. [104] high-gain Design of a  operational ampli er and other circuits by means of gen. prog. [93] high-level A GA appr. to  synthesis of digital circuits [204] { A gen. framework for the  opt. of low power VLSI DSP syst. [100] { A gen. -alg. -based  synthesis for partitioned bus architecture [286] { Integrated sch. , allocation and module sel. for designspace exploration in  synthesis [200]  synthesis of data paths for easy testability [206]  synthesis opt. with GAs [185]  synthesis sch. and allocation using GAs [173]  synthesis using GA [58] Hill climbing beats gen. search on a Boolean circuit synthesis problem of Koza's [87] human Four problems for which a computer prog. evolved by gen. prog. is competitive with  perf. [209] hybrid A  GA for the channel routing problem [49] { A  multilevel/gen. appr. for circuit partitioning [70] { Component sel. using  opt. alg. [150] { Fast and stable  GA for the ratio-cut partitioning problem on hypergraphs [45] { Minimisation of multioutput Reed-Muller binary decision diagrams using  GA. [238]  GA for the channel routing problem [132]  GAs with hyperplane synthesis: A theoretical and empirical study [145] { OFDD based minimization of xed polarity ReedMuller expressions using  GAs [120] { Restrictive channel routing with  GAs

[169] { VLSI standard-cell placement by par.  simulatedannealing and GA [123] hypercube GA for embedding a complete graph in a  with a VLSI appl. [150] hypergraphs Fast and stable hybrid GA for the ratiocut partitioning problem on  [132] hyperplane Hybrid GAs with  synthesis: A theoretical and empirical study [264] IC/MCM A perf. -driven  placement alg. featuring explicit design space exploration [68] Iddq Fast alg. for computing  tests for comb. circuits [101] identi cation Use of architecture-altering operations to dynamically adapt a three-way analog source  circuit to accommodate a new source [108] image A modi ed GA for extracting thermal pro les from infrared  data [195] immune A VLSI oorplan design based on gen.  recruitment mechanism [268] immune system An evol. opt. based on the  and its appl. to the VLSI oorplan design problem [33] implementation A neural network  for an electronic nose [164]  and evaluation of GAs for syst. partitioning [142] { Opt. techniques based on the use of GAs (GAs) for logic  on FPGAs [211] { Using GAs to automate syst.  in a novel threedimensional packaging technology [216] implemented Par. GAs  on transputers [62] industrial Overview of evol. syst. for  electronics [201] in uenced Timing  general-cell gen. oorplanner [322] Informatik Massiv par. e genetische Algorithmen, Beitrage zum Tag der  Erlangen 1993 [108] infrared A modi ed GA for extracting thermal pro les from  image data [278] instantaneous Estimation of maximum power and  current using a GA [282] integrated GA based appr. for  state assignment and

ip op sel. in nite stateBLmachine synthesis [320] { GAs for the opt. of  circuits synthesis [286]  sch. , allocation and module sel. for design-space exploration in high-level synthesis [127] integrated circuits GAs in computer aided design of  [136] intelligent GATTO: an  tool for automatic test pattern generation for digital circuits [99] { Syst. based  cntr. appl. to electronic test generation and diagnostics using FuzzyART and GAs [10] inter-cluster A GA for channel routing using  mutation [262] interface Next generation test generator (NGTG)  to automatic test equipment [44] interval Circuit worst-case tolerance analysis via solutions of  linear equations [95] { Gen. opt. of  mathematics-based sensitivity analysis of switching converters [95] { Gen. opt. of  mathematics-based sensitivity analysis of switching converters [82] inverse Appl. of a GA for evaluation of a quenching test by an  task with an unknown time constant of a sensor [125] Iterative [simulation-based gen. + deterministic techniques] = complete ATPG [58] Koza's Hill climbing beats gen. search on a Boolean circuit synthesis problem of  [158] layer GAs for partitioning, placement, and  assignment for multichip modules [155] { MCM  assignment using gen. search [53] layout Geep - a low-power GA  syst. [140] { Gen. beam search for gate matrix  [328] { Gen. beam search for gate matrix  [198] { Gen. -based rotation assignment in marco cell  [121] { On the synthesis of gate matrix  [265] { Geep: A low power GA  syst. [331] { Solving gate-matrix  problems by simulated evol. [161] { Towards opt. circuit  using advanced search techniques [306] layouts A GA for global improvement of macrocell  [112] Layout-Synthese Chip-Assembly Strategien bei der  nach Floorplan-Vorgaben [333] learning Evolving hardware with gen.  A rst step towards building a Darwin machine [207]  heuristics for OBDD minimization by evol. alg.

[330] level Applying simulated evol. to high  synthesis [235] { Gen. framework for the high  opt. of low power VLSI DSP syst. [334] levels Evolvable hardware { gen. based generation of electric circuitry at gate and hardware description language (HDL)  [40] LG Electronics Appl. of evol. computations at  [44] linear Circuit worst-case tolerance analysis via solutions of interval  equations [60] { Small-signal modelling for microwave FET  circuits based on a GA [26] Load Cell GA Opt. of  Geometry by Finite Element Analysis [37] Load cell shape opt. using GAs and nite element analysis [271] local Design elements of EHW using GA with  improvement of chromosomes [215] { Opt. of neighborhood size for par.  search and its appl. to test generation of combinational circuits [135] { State assignment for low-power FSM synthesis using gen.  search [43] LOCSTEP A logic simulation based test generation procedure [78, 250] logic Experiences of using evol. techniques in  minimisation [43] { LOCSTEP: A  simulation based test generation procedure [34] { Multilevel  synthesis using alg. based on nat. processes [35] { Neural technologies and GAs in modern  design [142] { Opt. techniques based on the use of GAs (GAs) for  impl. on FPGAs [277] { The derivation of minimal test sets for combinational  cuircuits using GAs [141] logic circuits A gen. appr. to test generation for  [41] logic functions Ternary decision diagram opt. of ReedMuller  using a GA for variable and simpli cation rule ordering [53] low-power Geep - a  GA layout syst. [50] { Gen. synthesis techniques for  digital signal processing circuits [256] { Gen. synthesis techniques for  digital signal processing circuits [135] { State assignment for  FSM synthesis using gen. local search [28] LSI chip Polycell placement for analog  designs by GAs and tabu search [333] machine Evolving hardware with gen. learning: A rst step towards building a Darwin  [133] machines Pioneer: A new tool for coding of multi-level nite state  based on evol. prog. [300] macro A GA for  cell placement [306] macrocell A GA for global improvement of  layouts [159] macro-cell A  global router based on two GAs [327]  and module placement by gen. adaptive search with bitmap-represented chromosome [156] { SAGA: a uni cation of the GA with simulated annealing and its appl. to  placement [317] macrocomponents Analogue placement by formulation of  and gen. partitioning [139, 154] Makrozellen Plazierung von  durch genetische Algorithmen auf verteilten und massiv par. en Rechnern [91] Manual APLACTM Circuit Simulation and Design Tool, User's  [222] manufacturing GA for low variance cntr. in semiconductor device  some early results [187] mapping Improved technology  using a new appr. to Boolean matching [198] marco cell Gen. -based rotation assignment in  layout [322] Massiv par. e genetische Algorithmen, Beitrage zum Tag der Informatik Erlangen 1993 [139, 154] { Plazierung von Makrozellen durch genetische Algorithmen auf verteilten und  par. en Rechnern [187] matching Improved technology mapping using a new appr. to Boolean  [95] mathematics-based Gen. opt. of interval  sensitivity analysis of switching converters [95] { Gen. opt. of interval  sensitivity analysis of switching converters [140] matrix Gen. beam search for gate  layout

[218] maximum A framework for estimating  powerdissipation in CMOS combinational circuits using GAs [278] { Estimation of  power and instantaneous current using a GA [144] MCM GA for  partitioning [155]  layer assignment using gen. search [191, 220] { Perf. -driven  partitioning through an adaptive GA [237] MCM/IC timing-driven placement alg. featuring explicit design space exploration [171] MCMs A GA-based circuit partitioner for  [64] meaningful Atomatic circuit simpli cation for  symbolic analysis using the GA [195] mechanism A VLSI oorplan design based on gen. immune recruitment  [323] meta-genetic A gen. appr. to standard cell placement using  parameter opt. [162] method Appl. of mutants as operators of GAs for optimising of VLSI and PCB elements placement on the basis of scanning area  [69] { Symbolic  for simplifying AND-EXOR Rep. of Boolean functions using a binary-decision technique and a GA [196] methodology Two-stage simulated annealing  [80] methods Non-exhaustive search  and their use in the minimization of Reed-Muller canonical expansions [223] { Stochastic  for transistor size opt. of CMOS VLSI circuits [178] microprocessor A par. GA for multi-objective  design [60] microwave Small-signal modelling for  FET linear circuits based on a GA [277] minimal The derivation of  test sets for combinational logic cuircuits using GAs [78, 250] minimisation Experiences of using evol. techniques in logic  [45]  of multioutput Reed-Muller binary decision diagrams using hybrid GA. [46] minimization A GA for 2-level AND/EXOR  [166] { A GA for  of xed polarity Reed-Muller expressions [207] { Learning heuristics for OBDD  by evol. alg. [80] { Non-exhaustive search methods and their use in the  of Reed-Muller canonical expansions [145] { OFDD based  of xed polarity Reed-Muller expressions using hybrid GAs [269] minimized Channel and switchbox routing with  crosstalk. A par. GA appr. [239] mixture Hierarchical strategy of model partitioning for VLSI-design using an improve  of experts appr. [276] model A GA for multiple fault  test generation for combinational VLSI circuits [239] { Hierarchical strategy of  partitioning for VLSI-design using an improve mixture of experts appr. [19] modeled HDL-prog. development  upon embryonic development [111] modeling ES in der Halbleitertechnik fur die Charakterisierung von MOS-bauelementen [Application of evol. strategy in semiconductor  for the characterization of MOSdevices] [60] modelling Small-signal  for microwave FET linear circuits based on a GA [97] models Using neural network process  to perform PECVD silicon dioxide recipe synthesis via GAs [35] modern Neural technologies and GAs in  logic design [108] modi ed A  GA for extracting thermal pro les from infrared image data [138]  gen. channel router [129] Modular scheme for designing special purpose associative memories and beyond [130] module A  placement using GAs [167] { An enhanced gen. formulation for sch. ,  allocation, and binding in VLSI design [279] { Enhanced gen. solution for sch. ,  allocation, and binding in VLSI design [137] { GAs for the  orientation problem [286] { Integrated sch. , allocation and  sel. for design-space exploration in high-level synthesis [327] { Macro-cell and  placement by gen. adaptive search with bitmap-represented chromosome [20] modules An evol. alg. for the routing of multi-chip  [111] MOS-bauelementen ES in der Halbleitertechnik fur die Charakterisierung von  [Application of evol. strategy

in semiconductor modeling for the characterization of MOSdevices] [111] MOS-devices ES in der Halbleitertechnik fur die Charakterisierung von MOS-bauelementen [Application of evol. strategy in semiconductor modeling for the characterization of  [73] motion Soft computing in power electronics and  cntr. [20] multi-chip An evol. alg. for the routing of  modules [158] multichip modules GAs for partitioning, placement, and layer assignment for  [34] Multilevel logic synthesis using alg. based on nat. processes [133] multi-level Pioneer: A new tool for coding of  nite state machines based on evol. prog. [55] { Restricted evaluation GAs with tabu search for opt. Boolean functions as  AND-EXOR networks [49] multilevel/genetic A hybrid  appr. for circuit partitioning [178] multi-objective A par. GA for  microprocessor design [253] { Structural synthesis of cell-based VLSI circuits using a  geentic alg. [247] { Structural synthesis of cell-based VLSI circuits using a  GA [45] multioutput Minimisation of  Reed-Muller binary decision diagrams using hybrid GA. [109] multistep Appl. of the evol. strategy to optimize  eld plates for high voltage planar pn-junctions [71] multivalued Design of  circuits using GAs [194] multiway Gen.  partitioning [162] mutants Appl. of  as operators of GAs for optimising of VLSI and PCB elements placement on the basis of scanning area method [10] mutation A GA for channel routing using inter-cluster  [117] Nachrichtentechnik Untersuchung uber die Anwendbarkeit der ES in der  [34] natural Multilevel logic synthesis using alg. based on  processes [215] neighborhood Opt. of  size for par. local search and its appl. to test generation of combinational circuits [311] network A distr. GA for standard cell placement on a  of workstations [27] { Automatic analogue  synthesis using GAs [42] { Obtaining symbolic  functions of large circuits - an algebraic appr. [312, 313] { Wolverines: standard cell placement on a  of workstations [94] networks Boolean  decomposition using GAs [205] { Synthesis of highly testable xed-polarity AND-XOR canonical  - A GA-based appr. [148] { Use of recurrent  and GAs for solving standard cell placement problem [35] Neural technologies and GAs in modern logic design [113] neural net GA design of  based electronic nose [33] neural network A  impl. for an electronic nose [116] { Gen. based training of two-layer, optoelectronic  [97] { Using  process models to perform PECVD silicon dioxide recipe synthesis via GAs [321] Neural networks and GAs as prog. paradigm for a new CMOS-array computer [81] { Recipe synthesis for PECVD SiO2 lms using  and GAs [262] Next generation test generator (NGTG) interface to automatic test equipment [262] NGTG Next generation test generator  interface to automatic test equipment [275] { Text generation test generator  for digital circuits [292] node partitioning GA for  problem and appl. in VLSI design [80] Non-exhaustive search methods and their use in the minimization of Reed-Muller canonical expansions [33] nose A neural network impl. for an electronic  [113] { GA design of neural net based electronic  [207] OBDD Learning heuristics for  minimization by evol. alg. [272] OBDD-based On opt. bist-architecture by using  appr. and GAs [47] OBDDs A GA for variable ordering of  [147] objectives GA for test sch. with dierent 

[42] Obtaining symbolic network functions of large circuits - an algebraic appr. [145] OFDD based minimization of xed polarity ReedMuller expressions using hybrid GAs [77] OKFDD circuits A GA for the construction of small and highly testable  [75] op amp Evol. of a 60 decibel  using gen. prog. [30] opamp DARWIN: CMOS  synthesis by means of a GA [104] operational ampli er Design of a high-gain  and other circuits by means of gen. prog. [101] operations Use of architecture-altering  to dynamically adapt a three-way analog source ident. circuit to accommodate a new source [79] { Use of automatically de ned functions and architecture-altering  in automated circuit synthesis using gen. prog. [162] operators Appl. of mutants as  of GAs for optimising of VLSI and PCB elements placement on the basis of scanning area method [115] optimal Adaptive GA for  printed circuit board assembly planning [107] { Appl. of gen. based alg. to  capacitor placement [102]  replacement strategies - GAs appr. [228] { On generating  signal probabilities for random tests: a gen. appr. [161] { Towards  circuit layout using advanced search techniques [204] optimisation A gen. framework for the high-level  of low power VLSI DSP syst. [31] { Combinational and sequential logic  using GAs [26] { GA  of Load Cell Geometry by Finite Element Analysis [235] { Gen. framework for the high level  of low power VLSI DSP syst. [95] { Gen.  of interval mathematics-based sensitivity analysis of switching converters [95] { Gen.  of interval mathematics-based sensitivity analysis of switching converters [206] { High-level synthesis  with GAs [37] { Load cell shape  using GAs and nite element analysis [41] { Ternary decision diagram  of Reed-Muller logic functions using a GA for variable and simpli cation rule ordering [162] optimising Appl. of mutants as operators of GAs for  of VLSI and PCB elements placement on the basis of scanning area method [221] optimization A cellular GA for the oorplan area  problem on a SIMD architecture [323] { A gen. appr. to standard cell placement using metagenetic parameter  [245] { An adaptive par. GA for VLSI-layout  [268] { An evol.  based on the immune syst. and its appl. to the VLSI oorplan design problem [70] { Component sel. using hybrid  alg. [219] { Constrained  with GAs: channel routing case [98] { Experimental study par. GA for placement  [153] { Floorplan area  using GAs [244] { GALLO: a GA for oorplan area  [128] { GA based design  of CMOS VLSI circuits [320] { GAs for the  of integrated circuits synthesis [51] { Gen.  in circuit simulation [66] { Gen.  of a fuzzy syst. for charging batteries [96] { Gen. based redundancy  [309]  by simulated evol. with appl. to standard cell placement [215]  of neighborhood size for par. local search and its appl. to test generation of combinational circuits [142]  techniques based on the use of GAs (GAs) for logic impl. on FPGAs [273] { On improving gen.  based test generation [267] { On the compaction of test sets produced by gen.  [197] { Perf. and area  of VLSI syst. using GAs [233] { Placement  using behavior based software agents and the GA [61] { Placement  using behavior-based software agents and the GA [291] { Standard Cell Routing  Using A GA [223] { Stochastic methods for transistor size  of CMOS VLSI circuits [72] { Syst. for  of electronic-circuits using GA [109] optimize Appl. of the evol. strategy to  multistep eld plates for high voltage planar pn-junctions

[122] { GAP: a GA appr. to  two-bit decoder PLAs [14] optimized GAs for thermosciences research: Appl. to the  cooling of electronic components [272] optimizing On  bist-architecture by using OBDDbased appr. and GAs [55] { Restricted evaluation GAs with tabu search for  Boolean functions as multi-level AND-EXOR networks [13] { Using a GA for  zed polarity Reed-Muller expansions of Boolean functions [116] optoelectronic Gen. based training of two-layer,  neural network [47] ordering A GA for variable  of OBDDs [84] { Improved variable  of BDDS with novel GA [41] { Ternary decision diagram opt. of Reed-Muller logic functions using a GA for variable and simpli cation rule  [25] { Using GAs for the variable  of Reed-Muller binary decision diagrams [137] orientation GAs for the module  problem [243] oriented TOGAPS: a testability  GA for pipeline synthesis [62] Overview of evol. syst. for industrial electronics [310] package Esp: A new standard cell placement  using simulated evol. [211] packaging Using GAs to automate syst. impl. in a novel three-dimensional  technology [321] paradigm Neural networks and GAs as prog.  for a new CMOS-array computer [151] parallel A  EP-based channel router [178] { A  GA for multi-objective microprocessor design [280] { A  GA for perf. -driven VLSI routing [241] { A  GA for two detailed routing problems [181] { A  gen. VLSI architecture for comb. real-time appl. - Disc sch. [245] { An adaptive  GA for VLSI-layout opt. [269] { Channel and switchbox routing with minimized crosstalk. A  GA appr. [98] { Experimental study  GA for placement opt. [288]  GA for channel routing [216]  GAs implemented on transputers [215] { Opt. of neighborhood size for  local search and its appl. to test generation of combinational circuits [126] { VLSI circuit synthesis using a  GA [169] { VLSI standard-cell placement by  hybrid simulatedannealing and GA [322] parallele Massiv  genetische Algorithmen, Beitrage zum Tag der Informatik Erlangen 1993 [139, 154] parallelen Plazierung von Makrozellen durch genetische Algorithmen auf verteilten und massiv  Rechnern [323] parameter A gen. appr. to standard cell placement using meta-genetic  opt. [86] parasitic GAs design of electronic analogue circuits including  eects [89] parasitic eects GA design of electronic analogue circuits including  [257, 260] Partial scan ip op sel. for simulation-based sequential ATPGs [100] partitioned A gen. -alg. -based high-level synthesis for  bus architecture [171] partitioner A GA-based circuit  for MCMs [168] partitioning An adaptive GA for VLSI circuit  [318] { An evol. -based appr. to  ASIC syst. [316] { Analog component placement by GAs | part I:  [317] { Analogue placement by formulation of macrocomponents and gen.  [150] { Fast and stable hybrid GA for the ratio-cut  problem on hypergraphs [144] { GA for MCM  [284] { GA for  circuits [158] { GAs for  placement, and layer assignment for multichip modules [194] { Gen. multiway  [239] { Hierarchical strategy of model  for VLSI-design using an improve mixture of experts appr. [164] { Impl. and evaluation of GAs for syst.  [191, 220] { Perf. -driven MCM  through an adaptive GA [200] paths High-level synthesis of data  for easy testability [134] patterns Generating test  for VLSI circuits using a GA [162] PCB Appl. of mutants as operators of GAs for optimising of VLSI and  elements placement on the basis of scanning area method [106]  assembly planning using GAs

[114] { Planning of component placement/insertion sequence and feeder setup in  assembly using GA [81] PECVD Recipe synthesis for  SiO2 lms using neural networks and GAs [97] { Using neural network process models to perform  silicon dioxide recipe synthesis via GAs [97] perform Using neural network process models to  PECVD silicon dioxide recipe synthesis via GAs [87] performance Four problems for which a computer prog. evolved by gen. prog. is competitive with human  [197]  and area opt. of VLSI syst. using GAs [199]  driven standard-cell placement using the GA [280] performance-driven A par. GA for  VLSI routing [264] { A  IC/MCM placement alg. featuring explicit design space exploration [332]  global routing based on simulated evol. [191, 220]  MCM partitioning through an adaptive GA [227] physical A GA for VLSI  design automation [212] { GAs appl. to the  design of VLSI circuits: A survey [225] { VLSI  Design Automation, Theory and Practice [193] { VLSI  Design Automaton: Theory and Practice [133] Pioneer A new tool for coding of multi-level nite state machines based on evol. prog. [243] pipeline TOGAPS: a testability oriented GA for  synthesis [255] pipelined Synthesis of testable  datapaths using gen. search [32] placement A comparison of EP and GAs for electronic part  [311] { A distr. GA for standard cell  on a network of workstations [305] { A feasibility study of gen.  [300] { A GA for macro cell  [130] { A module  using GAs [264] { A perf. -driven IC/MCM  alg. featuring explicit design space exploration [17] { A study on appl. of GA to automatic  of parts on printed circuit boards [316] { Analog component  by GAs | part I: Partitioning [317] { Analogue  by formulation of macrocomponents and gen. partitioning [107] { Appl. of gen. based alg. to opt. capacitor  [162] { Appl. of mutants as operators of GAs for optimising of VLSI and PCB elements  on the basis of scanning area method [184] { Cell  by GA [98] { Experimental study par. GA for  opt. [158] { GAs for partitioning,  and layer assignment for multichip modules [293, 294] { Gen.  [327] { Macro-cell and module  by gen. adaptive search with bitmap-represented chromosome [237] { MCM/IC timing-driven  alg. featuring explicit design space exploration [233]  opt. using behavior based software agents and the GA [61]  opt. using behavior-based software agents and the GA [309] { Opt. by simulated evol. with appl. to standard cell  [199] { Perf. driven standard-cell  using the GA [28] { Polycell  for analog LSI chip designs by GAs and tabu search [156] { SAGA: a uni cation of the GA with simulated annealing and its appl. to macro-cell  [310] { Esp: A new standard cell  package using simulated evol. [308] { Esp:  by simulated evol. [325] { Gasp - a GA for standard cell  [324] { Standard Cell  and the GA [176] { Timing driven GA for standard-cell  [326] { VLSI cell  techniques [169] { VLSI standard-cell  by par. hybrid simulatedannealing and GA [312, 313] { Wolverines: standard cell  on a network of workstations [114] placement/insertion Planning of component  sequence and feeder setup in PCB assembly using GA [109] planar Appl. of the evol. strategy to optimize multistep eld plates for high voltage  pn-junctions [114] Planning of component placement/insertion sequence and feeder setup in PCB assembly using GA [106] { PCB assembly  using GAs [122] PLAs GAP: a GA appr. to optimize two-bit decoder 

[109] plates Appl. of the evol. strategy to optimize multistep eld  for high voltage planar pn-junctions [303] PLAYOUT Chip assembly in the  VLSI design syst. [139, 154] Plazierung von Makrozellen durch genetische Algorithmen auf verteilten und massiv par. en Rechnern [109] pn-junctions Appl. of the evol. strategy to optimize multistep eld plates for high voltage planar  [166] polarity A GA for minimization of xed  Reed-Muller expressions [145] { OFDD based minimization of xed  Reed-Muller expressions using hybrid GAs [13] { Using a GA for opt. zed  Reed-Muller expansions of Boolean functions [28] Polycell placement for analog LSI chip designs by GAs and tabu search [204] power A gen. framework for the high-level opt. of low  VLSI DSP syst. [278] { Estimation of maximum  and instantaneous current using a GA [235] { Gen. framework for the high level opt. of low  VLSI DSP syst. [265] { Geep: A low  GA layout syst. [73] { Soft computing in  electronics and motion cntr. [218] powerdissipation A framework for estimating maximum  in CMOS combinational circuits using GAs [203, 261] presence A GA for VLSI channel routing in the  of cyclic vertical constraints [115] printed circuit board Adaptive GA for opt.  assembly planning [17] printed circuit boards A study on appl. of GA to automatic placement of parts on  [228] probabilities On generating opt. signal  for random tests: a gen. appr. [221] problem A cellular GA for the oorplan area opt.  on a SIMD architecture [268] { An evol. opt. based on the immune syst. and its appl. to the VLSI oorplan design  [287] { Applying GAs to the state assignment  a case study [160] { Designing GAs for the state assignment  [299] { Distr. GAs for the oorplan design  [150] { Fast and stable hybrid GA for the ratio-cut partitioning  on hypergraphs [292] { GA for node partitioning  and appl. in VLSI design [137] { GAs for the module orientation  [238] { Hybrid GA for the channel routing  [87] problems Four  for which a computer prog. evolved by gen. prog. is competitive with human perf. [331] { Solving gate-matrix layout  by simulated evol. [165] problem-space Datapath synthesis using a  GA [43] procedure LOCSTEP: A logic simulation based test generation  [24] process Automatic hardware design with an evol.  [97] { Using neural network  models to perform PECVD silicon dioxide recipe synthesis via GAs [34] processes Multilevel logic synthesis using alg. based on nat.  [50] processing Gen. synthesis techniques for low-power digital signal  circuits [267] produced On the compaction of test sets  by gen. opt. [108] pro les A modi ed GA for extracting thermal  from infrared image data [143] programmable Selecting  space compactors for BIST using GAs [32] programming A comparison of evol.  and GAs for electronic part placement [103] { Automated synthesis of computational circuits using gen.  [321] { Neural networks and GAs as  paradigm for a new CMOS-array computer [133] { Pioneer: A new tool for coding of multi-level nite state machines based on evol.  [151] programming-based A par. evol.  channel router [214] Prototyping of VLSI components from a formal speci cation [296] punctuated GAs and  equilibria in VLSI [82] quenching Appl. of a GA for evaluation of a  test by an inverse task with an unknown time constant of a sensor [163] RAM-based TRACER-fpga: a router for  FPGA's [232] random Built-in multiple weighted  testing based on GAs

[228] { On generating opt. signal probabilities for  tests: a gen. appr. [76] random number generation Systolic  for GAs [297] randomly Compacting  generated test sets [298] { Gate - A GA for compacting  generated test sets [150] ratio-cut Fast and stable hybrid GA for the  partitioning problem on hypergraphs [181] real-time A par. gen. VLSI architecture for comb.  appl. - Disc sch. [139, 154] Rechnern Plazierung von Makrozellen durch genetische Algorithmen auf verteilten und massiv par. en  [81] Recipe synthesis for PECVD SiO2 lms using neural networks and GAs [97] { Using neural network process models to perform PECVD silicon dioxide  synthesis via GAs [39] recon guration Run time  of FPGA for scanning genomic databases [195] recruitment A VLSI oorplan design based on gen. immune  mechanism [148] recurrent Use of  networks and GAs for solving standard cell placement problem [92] redesign Digital  of continuous syst. with improved suitability using GAs [192] reduction A gen. appr. to test appl. time  for full scan circuits [96] redundancy Gen. based  opt. [166] Reed-Muller A GA for minimization of xed polarity  expressions [45] { Minimisation of multioutput  binary decision diagrams using hybrid GA. [80] { Non-exhaustive search methods and their use in the minimization of  canonical expansions [41] { Ternary decision diagram opt. of  logic functions using a GA for variable and simpli cation rule ordering [13] { Using a GA for opt. zed polarity  expansions of Boolean functions [25] { Using GAs for the variable ordering of  binary decision diagrams [145] Reed-Muller expressions OFDD based minimization of xed polarity  using hybrid GAs [172, 217] reference Hierarchical test pattern generation using a GA with a dynamic global  table [102] replacement Opt.  strategies - GAs appr. [69] representations Symbolic method for simplifying AND-EXOR  of Boolean functions using a binary-decision technique and a GA [14] research GAs for thermosciences  Appl. to the optimized cooling of electronic components [55] Restricted evaluation GAs with tabu search for opt. Boolean functions as multi-level AND-EXOR networks [118] Restrictive channel routing with evol. prog. [120]  channel routing with hybrid GAs [198] rotation Gen. -based  assignment in marco cell layout [301] router A detailed  based on simulated evol. [159] { A macro-cell global  based on two GAs [11] { Gen. channel  [138] { Modi ed gen. channel  [302] { SILK: Simulated evol.  [163] { TRACER-fpga: a  for RAM-based FPGA's [304] routing A GA for the  of VLSI circuits [280] { A par. GA for perf. -driven VLSI  [20] { An evol. alg. for the  of multi-chip modules [269] { Channel and switchbox  with minimized crosstalk. A par. GA appr. [189] { New GA for single row  [83] { New gen. single-layer  alg. for analog transistor arrays [332] { Perf. -driven global  based on simulated evol. [291] { Standard Cell  Opt. Using A GA [254] routing problem GASBOR: a GA appr. for solving the switchbox  [241] routing problems A par. GA for two detailed  [182] routing-problems Genrouter: a GA for channel  [189] row New GA for single  routing [179] RTL level test generation using GA and simulated annealing [41] rule Ternary decision diagram opt. of Reed-Muller logic functions using a GA for variable and simpli cation  ordering [39] Run time recon guration of FPGA for scanning genomic databases [156] SAGA a uni cation of the GA with simulated annealing and its appl. to macro-cell placement

[192] scan A gen. appr. to test appl. time reduction for full  circuits [257, 260] { Partial  ip op sel. for simulation-based sequential ATPGs [252] scan path GAs for  design [162] scanning Appl. of mutants as operators of GAs for optimising of VLSI and PCB elements placement on the basis of  area method [39] { Run time recon guration of FPGA for  genomic databases [167] scheduling An enhanced gen. formulation for  module allocation, and binding in VLSI design [279] { Enhanced gen. solution for  module allocation, and binding in VLSI design [147] { GA for test  with dierent objectives [146] { Gen.  of task graphs [185] { High-level synthesis  and allocation using GAs [286] { Integrated  allocation and module sel. for designspace exploration in high-level synthesis [315] scheme A simulation-based test generation  using GAs [129] { Modular  for designing special purpose associative memories and beyond [149] search A new variable step-size alg. using gen. -type  [140] { Gen. beam  for gate matrix layout [58] { Hill climbing beats gen.  on a Boolean circuit synthesis problem of Koza's [327] { Macro-cell and module placement by gen. adaptive  with bitmap-represented chromosome [155] { MCM layer assignment using gen.  [80] { Non-exhaustive  methods and their use in the minimization of Reed-Muller canonical expansions [215] { Opt. of neighborhood size for par. local  and its appl. to test generation of combinational circuits [135] { State assignment for low-power FSM synthesis using gen. local  [255] { Synthesis of testable pipelined datapaths using gen.  [161] { Towards opt. circuit layout using advanced  techniques [105] searching Evol. al  for circuit structures [143] Selecting prog. mable space compactors for BIST using GAs [70] selection Component  using hybrid opt. alg. [282] { GA based appr. for integrated state assignment and

ip op  in nite stateBLmachine synthesis [286] { Integrated sch. , allocation and module  for designspace exploration in high-level synthesis [257, 260] { Partial scan ip op  for simulation-based sequential ATPGs [111] semiconductor ES in der Halbleitertechnik fur die Charakterisierung von MOS-bauelementen [Application of evol. strategy in  modeling for the characterization of MOSdevices] [222] { GA for low variance cntr. in  device manufacturing: some early results [95] sensitivity Gen. opt. of interval mathematics-based  analysis of switching converters [95] sensitivity analysis Gen. opt. of interval mathematics-based  of switching converters [82] sensor Appl. of a GA for evaluation of a quenching test by an inverse task with an unknown time constant of a  [114] sequence Planning of component placement/insertion  and feeder setup in PCB assembly using GA [210] sequences Automatic test generation using gen. engineered distinguishing  [85] sequencing A GA for data  [281] { GA for data  [236] sequential Advanced techniques for GA-based  ATPGs [240] { Alternating strategies for  circuit ATPG [152] { An automatic test pattern generator for large  circuits based on GAs [22] { Appl. of simple GA to  circuit test generation [224] { Automatic test vector cultivation for  VLSI circuits using GAs [319] { CRIS: A test cultivation prog. for  VLSI circuits [15]  circuit test generation in a GA framework [257, 260] { Partial scan ip op sel. for simulation-based  ATPGs [266] sequential circuit A GA for  test generation based on symbolic fault simulation

[175] { Combining deterministic and gen. appr. for  test generation [285] sequential circuits Automatic test pattern generation for  using GAs [248] { Gatto: a GA for automatic test pattern generation for large synchronous  [31] sequential logic Combinational and  opt. using GAs [297] sets Compacting randomly generated test  [298] { Gate - A GA for compacting randomly generated test  [277] { The derivation of minimal test  for combinational logic cuircuits using GAs [114] setup Planning of component placement/insertion sequence and feeder  in PCB assembly using GA [37] shape Load cell  opt. using GAs and nite element analysis [50] signal Gen. synthesis techniques for low-power digital  processing circuits [228] { On generating opt.  probabilities for random tests: a gen. appr. [256] signal processing Gen. synthesis techniques for lowpower digital  circuits [74] Silicon evol. [97] silicon dioxide Using neural network process models to perform PECVD  recipe synthesis via GAs [302] SILK Simulated evol. router [221] SIMD architecture A cellular GA for the oorplan area opt. problem on a  [57] Si-MOSFETs Evol. alg. for the calculation of electron distributions in  [64] simpli cation Atomatic circuit  for meaningful symbolic analysis using the GA [41] { Ternary decision diagram opt. of Reed-Muller logic functions using a GA for variable and  rule ordering [69] simplifying Symbolic method for  AND-EXOR Rep. of Boolean functions using a binary-decision technique and a GA [301] simulated A detailed router based on  evol. [330] { Applying  evol. to high level synthesis [309] { Opt. by  evol. with appl. to standard cell placement [332] { Perf. -driven global routing based on  evol. [310] { Esp: A new standard cell placement package using  evol. [308] { Esp: Placement by  evol. [302] { SILK:  evol. router [331] { Solving gate-matrix layout problems by  evol. [179] simulated annealing RTL level test generation using GA and  [156] { SAGA: a uni cation of the GA with  and its appl. to macro-cell placement [196] { Two-stage  methodology [169] simulated-annealing VLSI standard-cell placement by par. hybrid  and GA [266] simulation A GA for sequential circuit test generation based on symbolic fault  [91] { APLACTM Circuit  and Design Tool, User's Manual [51] { Gen. opt. in circuit  [43] { LOCSTEP: A logic  based test generation procedure [315] simulation-based A  test generation scheme using GAs [125] { Iterative  gen. + deterministic techniques] = complete ATPG [257, 260] { Partial scan ip op sel. for  sequential ATPGs [56] simulator GA and  speed up electronic design process [189] single New GA for  row routing [83] single-layer New gen.  routing alg. for analog transistor arrays [63] single-stage A GA for determining facility design and con guration of  exible electronic assembly syst. [81] SiO2 Recipe synthesis for PECVD  lms using neural networks and GAs [215] size Opt. of neighborhood  for par. local search and its appl. to test generation of combinational circuits [223] { Stochastic methods for transistor  opt. of CMOS VLSI circuits [170] sizing The GA appl. to gate  [60] Small-signal modelling for microwave FET linear circuits based on a GA [54] SMD Balancing  assembly lines with GAs [183] Soft computing appr. to hardware software codesign [73]  in power electronics and motion cntr.

[233] software Placement opt. using behavior based  agents and the GA [61] { Placement opt. using behavior-based  agents and the GA [183] { Soft computing appr. to hardware  codesign [279] solution Enhanced gen.  for sch. , module allocation, and binding in VLSI design [44] solutions Circuit worst-case tolerance analysis via  of interval linear equations [331] Solving gate-matrix layout problems by simulated evol. [101] source Use of architecture-altering operations to dynamically adapt a three-way analog  ident. circuit to accommodate a new  [264] space A perf. -driven IC/MCM placement alg. featuring explicit design  exploration [249] { Design  exploration using the GA [237] { MCM/IC timing-driven placement alg. featuring explicit design  exploration [143] space compactors Selecting prog. mable  for BIST using GAs [214] speci cation Prototyping of VLSI components from a formal  [56] speed up GA and simulator  electronic design process [150] stable Fast and  hybrid GA for the ratio-cut partitioning problem on hypergraphs [324] Standard Cell Placement and the GA [291]  Cell Routing Opt. Using A GA [309] { Opt. by simulated evol. with appl. to  cell placement [310] { Esp: A new  cell placement package using simulated evol. [325] { Gasp - a GA for  cell placement [312, 313] { Wolverines:  cell placement on a network of workstations [311] standard cell A distr. GA for  placement on a network of workstations [323] standard cell placement A gen. appr. to  using meta-genetic parameter opt. [148] standard cell placement problem Use of recurrent networks and GAs for solving  [199] standard-cell Perf. driven  placement using the GA [176] { Timing driven GA for  placement [169] { VLSI  placement by par. hybrid simulated-annealing and GA [287] state Applying GAs to the  assignment problem: a case study [160] { Designing GAs for the  assignment problem [282] { GA based appr. for integrated  assignment and

ip op sel. in nite stateBLmachine synthesis [135]  assignment for low-power FSM synthesis using gen. local search [36]  assignment of nite state machines using aGA [133] { Pioneer: A new tool for coding of multi-level nite  machines based on evol. prog. [90] status Evol. design of analogue electronic circuits; current  [333] step Evolving hardware with gen. learning: A rst  towards building a Darwin machine [149] step-size A new variable  alg. using gen. -type search [223] Stochastic methods for transistor size opt. of CMOS VLSI circuits [112] Strategien Chip-Assembly  bei der Layout-Synthese nach Floorplan-Vorgaben [240] strategies Alternating  for sequential circuit ATPG [102] { Opt. replacement  - GAs appr. [239] strategy Hierarchical  of model partitioning for VLSIdesign using an improve mixture of experts appr. [259, 234] Structral cell-based VLSI circuit design using a GA [253] Structural synthesis of cell-based VLSI circuits using a multi-objective geentic alg. [247]  synthesis of cell-based VLSI circuits using a multiobjective GA [186] structure Design of a compact cluster  by using GAs [105] structures Evol. al searching for circuit  [230] subcircuit SURGEN: agen. appr. for  extraction [92] suitability Digital redesign of continuous syst. with improved  using GAs [230] SURGEN agen. appr. for subcircuit extraction [212] survey GAs appl. to the physical design of VLSI circuits: A  [269] switchbox Channel and  routing with minimized crosstalk. A par. GA appr.

[254] { GASBOR: a GA appr. for solving the  routing problem [95] switching Gen. opt. of interval mathematics-based sensitivity analysis of  converters [95] { Gen. opt. of interval mathematics-based sensitivity analysis of  converters [266] symbolic A GA for sequential circuit test generation based on  fault simulation [64] { Atomatic circuit simpli cation for meaningful  analysis using the GA [258] { Comparing topological,  and GA-based ATPGs: an experimental appr. [69]  method for simplifying AND-EXOR Rep. of Boolean functions using a binary-decision technique and a GA [42] { Obtaining  network functions of large circuits - an algebraic appr. [248] synchronous Gatto: a GA for automatic test pattern generation for large  sequential circuits [93] synthesis A GA appr. to high-level  of digital circuits [100] { A gen. -alg. -based high-level  for partitioned bus architecture [213] { Allocation and binding in data path  using a GA appr. [67] { An evol. appr. to syst. -level  [330] { Applying simulated evol. to high level  [103] { Automated  of computational circuits using gen. prog. [27] { Automatic analogue network  using GAs [124] { Circuit  through gen. prog. [38] { DARWIN: analogue circuit  based on GAs [30] { DARWIN: CMOS opamp  by means of a GA [165] { Datapath  using a problem-space GA [231, 246] { Evol.  of current-mode CMOS 4-valued circuits [282] { GA based appr. for integrated state assignment and

ip op sel. in nite stateBLmachine  [320] { GAs for the opt. of integrated circuits  [50] { Gen.  techniques for low-power digital signal processing circuits [256] { Gen.  techniques for low-power digital signal processing circuits [200] { High-level  of data paths for easy testability [206] { High-level  opt. with GAs [185] { High-level  sch. and allocation using GAs [173] { High-level  using GA [132] { Hybrid GAs with hyperplane  A theoretical and empirical study [286] { Integrated sch. , allocation and module sel. for designspace exploration in high-level  [34] { Multilevel logic  using alg. based on nat. processes [205]  of highly testable xed-polarity AND-XOR canonical networks - A GA-based appr. [255]  of testable pipelined datapaths using gen. search [121] { On the  of gate matrix layout [81] { Recipe  for PECVD SiO2 lms using neural networks and GAs [135] { State assignment for low-power FSM  using gen. local search [253] { Structural  of cell-based VLSI circuits using a multiobjective geentic alg. [247] { Structural  of cell-based VLSI circuits using a multiobjective GA [243] { TOGAPS: a testability oriented GA for pipeline  [79] { Use of automatically de ned functions and architecture-altering operations in automated circuit  using gen. prog. [97] { Using neural network process models to perform PECVD silicon dioxide recipe  via GAs [126] { VLSI circuit  using a par. GA [188] synthesizing Ecient alg. for analyzing and  faulttolerant datapaths [67] system-level An evol. appr. to  synthesis [76] Systolic random number generation for GAs [172, 217] table Hierarchical test pattern generation using a GA with a dynamic global reference  [28] tabu search Polycell placement for analog LSI chip designs by GAs and  [55] { Restricted evaluation GAs with  for opt. Boolean functions as multi-level AND-EXOR networks [322] Tag Massiv par. e genetische Algorithmen, Beitrage zum  der Informatik Erlangen 1993 [82] task Appl. of a GA for evaluation of a quenching test by an inverse  with an unknown time constant of a sensor [146] { Gen. sch. of  graphs

[236] techniques Advanced  for GA-based sequential ATPGs [48] { Evol.  for fault tolerance [78, 250] { Experiences of using evol.  in logic minimisation [18] { GA  for 3-valued transistor design [50] { Gen. synthesis  for low-power digital signal processing circuits [256] { Gen. synthesis  for low-power digital signal processing circuits [125] { Iterative [simulation-based gen. + deterministic  = complete ATPG [142] { Opt.  based on the use of GAs (GAs) for logic impl. on FPGAs [161] { Towards opt. circuit layout using advanced search  [326] { VLSI cell placement  [35] technologies Neural  and GAs in modern logic design [187] technology Improved  mapping using a new appr. to Boolean matching [211] { Using GAs to automate syst. impl. in a novel threedimensional packaging  [41] Ternary decision diagram opt. of Reed-Muller logic functions using a GA for variable and simpli cation rule ordering [276] test A GA for multiple fault model  generation for combinational VLSI circuits [263] { A GA framework for  generation [192] { A gen. appr. to  appl. time reduction for full scan circuits [315] { A simulation-based  generation scheme using GAs [82] { Appl. of a GA for evaluation of a quenching  by an inverse task with an unknown time constant of a sensor [22] { Appl. of simple GA to sequential circuit  generation [210] { Automatic  generation using gen. -engineered distinguishing sequences [224] { Automatic  vector cultivation for sequential VLSI circuits using GAs [175] { Combining deterministic and gen. appr. for sequential circuit  generation [297] { Compacting randomly generated  sets [319] { CRIS: A  cultivation prog. for sequential VLSI circuits [134] { Generating  patterns for VLSI circuits using a GA [147] { GA for  sch. with dierent objectives [229] { Gen. -alg. -based  generation for current testing of bridging faults in CMOS VLSI circuits [43] { LOCSTEP: A logic simulation based  generation procedure [262] { Next generation  generator (NGTG) interface to automatic  equipment [180]  generation for current testing of bridging faults in CMOS VLSI circuits [273] { On improving gen. opt. based  generation [215] { Opt. of neighborhood size for par. local search and its appl. to  generation of combinational circuits [179] { RTL level  generation using GA and simulated annealing [298] { Gate - A GA for compacting randomly generated  sets [15] { Sequential circuit  generation in a GA framework [99] { Syst. based intelligent cntr. appl. to electronic  generation and diagnostics using FuzzyART and GAs [190] { Syst. design for  using a gen. based hierarchical ATPG syst. [275] { Text generation  generator (NGTG) for digital circuits [277] { The derivation of minimal  sets for combinational logic cuircuits using GAs [88] { Transitional delay fault  generation using a GA [266] test generation A GA for sequential circuit  based on symbolic fault simulation [141] { A gen. appr. to  for logic circuits [152] test pattern An automatic  generator for large sequential circuits based on GAs [285] { Automatic  generation for sequential circuits using GAs [136] { GATTO: an intelligent tool for automatic  generation for digital circuits [172, 217] { Hierarchical  generation using a GA with a dynamic global reference table [248] { Gatto: a GA for automatic  generation for large synchronous sequential circuits [242] test patterns Generating  for VLSI circuits using a GA

[267] test sets On the compaction of  produced by gen. opt. [200] testability High-level synthesis of data paths for easy  [243] { TOGAPS: a  oriented GA for pipeline synthesis [77] testable A GA for the construction of small and highly  OKFDD circuits [205] { Synthesis of highly  xed-polarity AND-XOR canonical networks - A GA-based appr. [255] { Synthesis of  pipelined datapaths using gen. search [232] testing Built-in multiple weighted random  based on GAs [229] { Gen. -alg. -based test generation for current  of bridging faults in CMOS VLSI circuits [180] { Test generation for current  of bridging faults in CMOS VLSI circuits [68] tests Fast alg. for computing Iddq  for comb. circuits [228] { On generating opt. signal probabilities for random  a gen. appr. [275] Text generation test generator (NGTG) for digital circuits [132] theoretical Hybrid GAs with hyperplane synthesis: A  and empirical study [225] Theory VLSI Physical Design Automation,  and Practice [193] { VLSI Physical Design Automaton:  and Practice [108] thermal A modi ed GA for extracting  pro les from infrared image data [14] thermosciences GAs for  research: Appl. to the optimized cooling of electronic components [211] three-dimensional Using GAs to automate syst. impl. in a novel  packaging technology [101] three-way Use of architecture-altering operations to dynamically adapt a  analog source ident. circuit to accommodate a new source [192] time A gen. appr. to test appl.  reduction for full scan circuits [82] { Appl. of a GA for evaluation of a quenching test by an inverse task with an unknown  constant of a sensor [39] { Run  recon guration of FPGA for scanning genomic databases [176] Timing driven GA for standard-cell placement [201]  in uenced general-cell gen. oorplanner [237] timing-driven MCM/IC  placement alg. featuring explicit design space exploration [274] Timing-in uenced general-cell gen. oorplanner [243] TOGAPS a testability oriented GA for pipeline synthesis [44] tolerance Circuit worst-case  analysis via solutions of interval linear equations [48] { Evol. techniques for fault  [91] Tool APLACTM Circuit Simulation and Design  User's Manual [136] { GATTO: an intelligent  for automatic test pattern generation for digital circuits [133] { Pioneer: A new  for coding of multi-level nite state machines based on evol. prog. [258] topological Comparing  symbolic and GA-based ATPGs: an experimental appr. [59] topology Automated WYSIWYG design of both the  and component values of electrical circuits using gen. prog. [163] TRACER-fpga a router for RAM-based FPGA's [116] training Gen. based  of two-layer, optoelectronic neural network [18] transistor GA techniques for 3-valued  design [83] { New gen. single-layer routing alg. for analog  arrays [223] { Stochastic methods for  size opt. of CMOS VLSI circuits [88] Transitional delay fault test generation using a GA [251]  gate delay detection for combinational circuits using a GA [216] transputers Par. GAs implemented on  [122] two-bit GAP: a GA appr. to optimize  decoder PLAs [116] two-layer Gen. based training of  optoelectronic neural network [196] Two-stage simulated annealing methodology [156] uni cation SAGA: a  of the GA with simulated annealing and its appl. to macro-cell placement [82] unknown Appl. of a GA for evaluation of a quenching test by an inverse task with an  time constant of a sensor [117] Untersuchung uber die Anwendbarkeit der ES in der Nachrichtentechnik

[59] values Automated WYSIWYG design of both the topology and component  of electrical circuits using gen. prog. [47] variable A GA for  ordering of OBDDs [149] { A new  step-size alg. using gen. -type search [84] { Improved  ordering of BDDS with novel GA [41] { Ternary decision diagram opt. of Reed-Muller logic functions using a GA for  and simpli cation rule ordering [25] { Using GAs for the  ordering of Reed-Muller binary decision diagrams [222] variance GA for low  cntr. in semiconductor device manufacturing: some early results [224] vector Automatic test  cultivation for sequential VLSI circuits using GAs [139, 154] verteilten Plazierung von Makrozellen durch genetische Algorithmen auf  und massiv par. en Rechnern [203, 261] vertical A GA for VLSI channel routing in the presence of cyclic  constraints [203, 261] VLSI A GA for  channel routing in the presence of cyclic vertical constraints [227] { A GA for  physical design automation [204] { A gen. framework for the high-level opt. of low power  DSP syst. [280] { A par. GA for perf. -driven  routing [181] { A par. gen.  architecture for comb. real-time appl. Disc sch. [195] { A  oorplan design based on gen. immune recruitment mechanism [168] { An adaptive GA for  circuit partitioning [167] { An enhanced gen. formulation for sch. , module allocation, and binding in  design [268] { An evol. opt. based on the immune syst. and its appl. to the  oorplan design problem [174] { An extended EP alg. for  channel routing [162] { Appl. of mutants as operators of GAs for optimising of  and PCB elements placement on the basis of scanning area method [303] { Chip assembly in the PLAYOUT  design syst. [279] { Enhanced gen. solution for sch. , module allocation, and binding in  design [283] { Evol. Alg. for  CAD [134] { Generating test patterns for  circuits using a GA [128] { GA based design opt. of CMOS  circuits [123] { GA for embedding a complete graph in a hypercube with a  appl. [292] { GA for node partitioning problem and appl. in  design [296] { GAs and punctuated equilibria in  [290] { GAs and  circuit design [235] { Gen. framework for the high level opt. of low power  DSP syst. [326]  cell placement techniques [126]  circuit synthesis using a par. GA [225] VLSI Physical Design Automation, Theory and Practice [193]  Physical Design Automaton: Theory and Practice [169] VLSI standard-cell placement by par. hybrid simulatedannealing and GA [214] { Prototyping of  components from a formal speci cation [259] VLSI circuit Structral cell-based  design using a GA [234] { Structural cell-based  design using a GA [157] VLSI circuits A GA for channel routing in  [276] { A GA for multiple fault model test generation for combinational  [304] { A GA for the routing of  [224] { Automatic test vector cultivation for sequential  using GAs [319] { CRIS: A test cultivation prog. for sequential  [242] { Generating test patterns for  using a GA [212] { GAs appl. to the physical design of  A survey [229] { Gen. -alg. -based test generation for current testing of bridging faults in CMOS  [223] { Stochastic methods for transistor size opt. of CMOS  [253] { Structural synthesis of cell-based  using a multiobjective geentic alg. [247] { Structural synthesis of cell-based  using a multiobjective GA [180] { Test generation for current testing of bridging faults in CMOS  [197] VLSI systems Perf. and area opt. of  using GAs [239] VLSI-design Hierarchical strategy of model partitioning for  using an improve mixture of experts appr. [245] VLSI-layout An adaptive par. GA for  opt.

on a network of  [177] VLSI-layouts Gen. design of  [109] voltage Appl. of the evol. strategy to optimize multi- [312, 313] { Wolverines: standard cell placement on a network step eld plates for high  planar pn-junctions [232] weighted Built-in multiple  random testing based on [44] of worst-case Circuit  tolerance analysis via solutions of GAs interval linear equations [312, 313] Wolverines standard cell placement on a network of workstations [59] WYSIWYG Automated  design of both the topology [311] workstations A distr. GA for standard cell placement and component values of electrical circuits using gen. prog.

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Notations

y(ref) = the bibliography item does not belong to my collection of genetic papers. (ref) = citation source code. ACM = ACM Guide to Computing Literature, EEA = Electrical & Electronics Abstracts, BA = Biological Abstracts, CCA = Computers & Control Abstracts, CTI = Current Technology Index, EI = The Engineering Index (A = Annual, M = Monthly), DAI = Dissertation Abstracts International, P = Index to Scienti c & Technical Proceedings, BackBib = Thomas Back's unpublished bibliography, Fogel/Bib = David Fogel's EA bibliography, etc * = only abstract seen. ? = data of this eld is missing (BiBTeX-format). The last eld in each reference item in Teletype font is the BiBTEXkey of the corresponding reference.

Appendix A

Abbreviations The following other abbreviations were used to compress the titles of articles in the permutation title index: AI Alg. AL ANN(s) Appl. Appr. Cntr. Coll. Comb. Conf. CS(s) Distr. Eng. EP ES Evol. ExS(s) FF(s) GA(s) Gen. GP Ident. Impl.

Int. ImPr JSS ML Nat. NN(s) Opt.

= International = Image Processing = Job Shop Scheduling = Machine Learning = Natural = Neural Net(work)(s) = Optimization, Optimal, = Optimizer(s), Optimierung OR = Operation(s) Research Par. = Parallel, Parallelism Perf. = Performance Pop. = Population(s), Populational(ly) Proc. = Proceedings Prog. = Programming, Program(s), Programmed Prob. = Problem(s) QAP = Quadratic Assignment Problem Rep. = Representation(s), Representational(ly) SA = Simulated Annealing Sch. = Scheduling, Schedule(s) Sel. = Selection, Selectionism Symp. = Symposium Syst. = System(s) Tech. = Technical, Technology TSP = Travel(l)ing Salesman Problem

= Arti cial Intelligence = Algorithm(s) = Arti cial Life = Arti cial Neural Net(work)(s) = Application(s), Applied = Approach(es) = Control, Controlled, = Controlling, Controller(s) = Colloquium = Combinatorial = Conference = Classi er System(s) = Distributed = Engineering = Evolutionary Programming = Evolutionsstrategie(n), = Evolution(ary) strategies = Evolution, Evolutionary = Expert System(s) = Fitness Function(s) = Genetic Algorithm(s) = Genetic(s), Genetical(ly) = Genetic Programming = Identi cation = Implementation(s)

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Appendix B

Bibliography entry formats footnotesize This documentation was prepared with LATEX and reproduced from camera-ready copy supplied by the editor. The ones who are familiar with BibTeX may have noticed that the references are printed using abbrv bibliography style and have no diculties in interpreting the entries. For those not so familiar with BibTeX are given the following formats of the most common entry types. The optional elds are enclosed by "[ ]" in the format description. Unknown elds are shown by "?". y after the entry means that neither the article nor the abstract of the article was available for reviewing and so the reference entry and/or its indexing may be more or less incomplete. Book: Author(s), Title, Publisher, Publisher's address, year.

Example

John H. Holland. Adaptation in Natural and Arti cial Systems. The University of Michigan Press, Ann Arbor, 1975.

Journal article: Author(s), Title, Journal, volume(number): rst page { last page, [month,] year. Example David E. Goldberg. Computer-aided gas pipeline operation using genetic algorithms and rule learning. Part I: Genetic algorithms in pipeline optimization. Engineering with Computers, 3(?):35{45, 1987. y.

Note: the number of the journal unknown, the article has not been seen. Proceedings article: Author(s), Title, editor(s) of the proceedings, Title of Proceedings, [volume,]

pages, location of the conference, date of the conference, publisher of the proceedings, publisher's address.

Example

John R. Koza. Hierarchical genetic algorithms operating on populations of computer programs. In N. S. Sridharan, editor, Eleventh International Joint Conference on Arti cial Intelligence (IJCAI-89), pages 768{774, Detroit, MI, 20.-25. August 1989. Morgan Kaufmann, Palo Alto, CA. y.

Technical report: Author(s), Title, type and number, institute, year. Example

Thomas Back, Frank Homeister, and Hans-Paul Schwefel. Applications of evolutionary algorithms. Technical Report SYS-2/92, University of Dortmund, Department of Computer Science, 1992.

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