Chapter 3: Enhancement of crystallization of hydrogenated

Chapter3: Enhancement of crystallization of hydrogenated amorphous siliconby a hydrogenplasmatreatment

71

3.6 SUMMARY Room temperatureexposureto a RF hydrogenplasmacan dramaticallyreduce the thermalbudgetfor the crystallizationof PECVD a-Si:H films. The hydrogenplasma treatmentchangesthe microstructureof the q-Si:Hat the surface,and depleteshydrogen from the surface of the film. The plasma treatment creates seed nuclei of microcrystalline silicon at the surface (30-40 nm) of the a-Si:H film which are characterizedby Si-H2 bonds at the surfacesof the crystallites.During the subsequent anneal at 600 °c, these crystallites grow till the grains touch each other leading to complete crystallization. The plasma treatment thereby enhances the overall crystallization rate as the nucleation step is bypassedin this case. In spite of the enhancednucleation density due the plasma treatment,the grain size of the blanket hydrogen-plasma-treated films wascomparableto that of the untreatedfilms. This techniquecan be usedto reducethe thermal budget for the fabrication of polysilicon thin-film transistorsas discussedin the next chapter.This effect can also be controlled spatially resulting in polycrystalline silicon and amorphoussilicon areason the same substrateand in chapter 5 we will discuss the fabrication of integrated amorphousandpolycrystallinetransistors.In addition,by this techniqueof masking,the nucleationin the amorphousfilms can be controlled so that the location of the grain boundariesin the final polysilicon film can be controlled and larger grains can be realized. In the next chapterwe will discussthe use of this property in improving the performanceof thin-film transistors.

"""',,~

Chapter3: Enhancementof crystallizationof hydrogenatedamorphoussilicon by a hydrogenplasmatreatment

72

REFERENCES [1] [2] [3] [4] [5] [6]

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-.

j

Chapter3: Enhancementof crystallizationof hydrogenatedamorphoussilicon by a hydrogenplasmatreatment [18]

[19] [20] [21] [22] [23] [24] [25] [26]

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[37]

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R. B. IversonandR. Reif, "Recrystallizationof amorphizedpolycrystallinesilicon films on SiO2: Temperaturedependence of the crystallizationparameters,"Journal of Applied Physics,vol. 62, pp. 1675-1681,1987. L. Csepregi,E. F. Kennedy,J. W. Mayer, andT. W. Sigmon,"Substrate-orientation dependence of the epitaxialregrowthratefrom Si-implantedamorphousSi," Journal of Applied Physics,vol. 49, pp. 3906-3911,1978. E. Ma, "Thin ,Film Transistorsfor Macroelectronics:Devices,Substratesand Processes,"Ph. D. Thesis,PrincetonUniversity,pp. 30-36, 1999. D. M. Moffatt, "Propertiesof glasssubstratesfor poly-Si AMLCD technology," Materials ResearchSocietySymposiumProceedings,vol. 377, pp. 871-876,1995. D. M. Moffatt, "Flat paneldisplaysubstrates,"Materials ResearchSocietySymposium Proceedings,vol. 345,pp. 163-174,1994. E. Ma, "Thin Film Transistorsfor Macroelectronics:Devices,Substratesand Processes,"Ph. D. Thesis,PrincetonUniversity,pp. 146, 1999. L. E. Katz, "Oxidation," in VLSI Technology,S. M. Sze,Ed., 2nd ed. Singapore: McGraw-Hill, 1988,pp. 128. H. A. Naseem,Departmentof ElectricalEngineering,University of Arkansas,personal communication,1997. Y.- B. Park and S.-W. Rhee,"Effect of hydrogenplasmaprecleaningon the removalof interfacial amorphouslayer in the chemicalvapordepositionof microcrystallinesilicon films on silicon oxide surface,"Applied PhysicsLetters,vol. 68, pp. 2219-2221,1996. T. Kamins,in Polycrystallinesilicon integratedcircuit applications,2nd ed. Boston: Kluwer AcademicPublishers,1988,pp. 68-69. K. L. Chiang,C. J. Dell' Oca,andF. N. Schwettrnann,"Optical evaluationof polycrystallinesilicon surfaceroughness,"Journal of ElectrochemicalSociety,vol. 126,pp. 2267-2269,1979. R. Swanepoel,"Determinationof the thicknessand optical constantsof amorphous silicon," J. Phys.E. Sci. Instrum.,vol. 16,pp. 1214-1222,1983. M. H. Brodsky,M. Cardona,andJ. J. Cuomo,"Infrared andRamanspectraof the silicon-hydrogenbondsin amorphoussilicon preparedby glow dischargeand sputtering,"PhysicalReviewB, vol. 16,pp. 3556-3571,1977. D. Eaglesham,Bell Laboratories,Murray Hill NJ,personalcommunication,1998. C. C. Tsai and H. Fritzsche,"Effect of annealingon the optical propertiesof plasma depositedamorphoushydrogenatedsilicon," Solar EnergyMaterials, vol. 1, pp. 29-42, 1979. K. Nakazawaand K. Tanaka,"Effect of substratetemperatureon recrystallizationof plasmachemicalvapordepositionamorphoussilicon films," Journal of Applied Physics,vol. 68, pp. 1029-1032,1990. J. Bloem, Journal of Crystal Growth,vol. 50, pp. 581,1980. J. N. Lee, Y. W. Choi, B. J. Lee, andB. T. Ahn, "Microwave-irtducedlow-temperature crystallization of amorphous siliconthin films,"Journalof AppliedPhysics,vol. 82,pp. 2918-2921,1997. M.-K. Ryu, S.-M. Hwang,T.-H. Kim, K.-B. Kim, and S.-H. Min, "The effect of surface nucleationon the evolution of crystallinemicrostructureduring solid phase crystallizationof amorphousSi films on SiO2," Applied PhysicsLetters,vol. 71, pp. 3063-3065,1997. Y. Z. Wang,S. J. Fonash,O. O. Awadelkarim,andT. Gu, "Crystallizationofa-Si:H on glassfor activelayersin thin film transistors:Effect of glasscoating,"Journal of ElectrochemicalSociety,vol. 146,pp. 299-305,1999.

~

Chapter3: Enhancementof crystallizationof hydrogenatedamorphoussilicon by a hydrogenplasmatreatment [38] [39]

[40] [41]

[42]

[43] [44] [45] [46] [47] [48] [49]

[50] [51]

[52] [53] [54]

74

"

M. Stutzmann,"Role of mechanicalstressin the light-induceddegradationof hydrogenatedamorphoussilicon," Applied PhysicsLetters,vol. 47, pp. 21-23, 1985. A. Szekeresand P. Danesh,"Mechanicalstressin SiO2/Sistructuresformedby the thermaloxidation of amorphousand crystallinesilicon," SemiconductorScienceand Technology,vol. 11,pp. 1225-1230,1996. T. Kamins,in Polycrystallinesiliconfor integratedcircuit applications,2nd ed. Boston:Kluwer, 1988,pp. 78-80. J. R. A. Carlsson,J.-E. Sundgren,X.-H. Li, L. D. Madsen,andH. T. G. Hentzell, "Predictingthe crystallizationtemperaturevariationwith compositionfor amorphous silicon-basedbinary alloy thin films," Journal of Applied Physics,vol. 81, pp. 11501156,1997. H. Gleskova,S. Wagner,andZ. Suo,"a-Si:H TFfs madeon polymide foil by PECVD at 150 °C," Materials ResearchSocietySymposiumProceedings,vol. 452, pp. 779-784, 1997. C. V. ThompsonandH. I. Smith, "Surface-energydriven secondarygrain growth in ultra-thin «100 nm) films of silicon," Applied PhysicsLetters,vol. 44, pp. 603-605, 1984. D. Pribat, P. Legagneux,F. Plais,C. Reita,F. Petinot,and o. Huet, "Low temperature polysilicon materialsand devices,"Materials ResearchSocietySymposium Proceedings,vol. 424, pp. 127-139,1997. ' L. Haji, P. Joubert,J. Stoemenos,andN. A. Economou,"Mode of growth and microstructureof polycrystallinesilicon obtainedby solid-phasecrystallizationof an amorphoussilicon film," Journal of Applied Physics,vol. 75, pp. 3944-3952,1994. H. Kakinuma,M. Mohri, M. Sakamoto,andT. Tsuruoka,"Structuralpropertiesof polycrystallinesilicon films preparedat low temperatureby plasmachemicalvapor deposition,"Journal of Applied Physics,vol. 70, pp. 7374-7381,1991. T. I. Kamins,Journal of ElectrochemicalSociety,vol. 127,pp. 686, 1980. P. Rai-ChoudhuryandD. K. Schroder,Journal of ElectrochemicalSociety,vol. 120, pp.664, 1973. P. R. i Cabarrocas,S. Hamma,andA. Hadjadj,"New featuresof the layer-by-layer depositionof microcrystallinesilicon films revealedby spectroscopicellipsometryand high resolutiontransmissionelectronmicroscopy,"Applied PhysicsLetters,vol. 69, pp. 529-531,1996. C. Godet,N. Layadi, andP. R. i. Cabarrocas,"Role of mobile hydrogenin the amorphoussilicon recrystallization,"Applied PhysicsLetters,vol. 66, pp. 3146-3148, 1995. ;' J.-H. Zhou, K. Ikuta, T. Yasuda,T. Umeda,S. Yamasaki,andK. Tanaka,"Growth of amorphous-layer-free microcrystallinesilicon on insulatingglasssubstratesby plasmaenhancedchemicalvapordeposition,"Applied PhysicsLetters,vol. 71, pp. 1534-1536, 1997. G. Radnoczi,A. Robertsson,H. T. G. Hentzell,S. F. Gong,andM.-A. H~san,"AI inducedcrystallizationof a-Si," Journal of Applied Physics,vol. 69, pp. 6394-6399, 1991. J. Hanna,H. Azuma,H. Shirai, M. Azuma,andI. Shimizu,"Atomic hydrogenimproves the rigidity of Si-networkandtail statesat the valencebandin a-Si:H anda-Si:H(F) films," Journal of Non-crystallineSolids,vol. 114,pp. 804-806,1989. E. Srinivasanand G. N. Parsons,"Hydrogeneliminationandphasetransitionsin pulsed-gasplasmadepositionof amorphousandmicrocrystallinesilicon," Journal of Applied Physics,vol. 81, pp. 2847-2855,1997.

"

I ,

~,..

Chapter hydrogen

[55]

3: Enhancement plasma

S. Ray,

S. C. De,

prepared

[56]

[57]

of crystallization

and A. K. Barua,

by the glow

Films,

vol.

R. A.

Street,

in Hydrogenated

Press,

1991,

pp.

E. F. Kennedy, 14N,

and

pp.

amorphous

silicon

by a

75

"Characterization

method

277-285,

under

of microcrystalline

different

deposition

silicon

conditions,"

films Thin

1988.

Amorphous

Silicon.

London:

Cambridge

University

334. L. Csepregi,

noble vol.

156,

discharge

Solid

Physics,

of hydrogenated

treatment

gases

J. W.

Mayer,

on the crystallization

and T. W.

Sigmon,

of amorphous

"Influence

Si layers,"

of Journal

160,

12C,

of Applied

48, pp. 4241-4246,1977.

.. '::

!\,

..

\

I

~

I

Chapter 4

POLY CRYSTALLINE SILICON THIN-FILM TRANSISTORS I i

I

4.1 INTRODUCTION The technologyusedto fabricatethin-film transistors(TFTs) in polycrystalline silicon (polysilicon) layers is similar to that used for fabrication of metal-oxidesemiconductor field-effect transistors (MOSFETs) in bulk silicon substrates. Conventional integrated circuits fabricated in bulk Si requires isolation between devices,which is usually achievedby growing thick oxidesor etchingtrenchesbetween the active device regions.In addition, the capacitivecoupling betweenthe integratedcircuit devices through the high-relative-permittivity silicon substratecan degrade circui~performance.Chargeinjected at one node of a circuit may travel to an another node through the substrate,changingthe chargestate of dynamic memory elements. Also charge generation in the substratealso makes bulk-silicon integrated circuits sensitiveto radiation. Building transistorsin thin polysilicon films isolated from the substrateby the oxide reducesall theselimitations. Restrictingintegratedcircuits to a singleplaneof devicesat the surfaceof a bulk silicon wafer limits the type of devicesand circuits that can be realized.The ability to use the third dimension by employing severallayers of transistorswould enable the

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Chapter4: Polycrystalline siliconthin-filmtransistors

77

fabricationof novel devicestructuresandthe increaseof the devicedensityon the chip. This should also reduce the interconnectionlength between the devices, improving overall circuit speed.TFTs on large-area,preferablytransparentsubstrateswill also be useful for display applications,both for active-matrixtransistorarray and for addressing and otherperipheralcircuitry. Although the shapeof the polysilicon TFT characteristicsis comparableto that of a bulk MOSFET, a large gatevoltagemustbe appliedbeforesignificant drain current can flow; the thresholdvoltage is high, and the transistorhas a low transconductance. This is causeddue the high concentrationof traps, which arise from the crystalline defectsin the polysilicon, especiallyat the grain boundaries,within the forbiddengap of the polysilicon. Much of the applied gate voltage is used to chargeor dischargethese traps,ratherthan inducing free carriersin an inversionlayer, leadingto higher threshold voltages1. As most of the traps are locatednearthe grain boundaries,the transistorcan be visualized as several transistors in series. Comparatively high-quality grains are separatedfrom each other by highly defective grain boundaries.Consequently,the transistorover the central regionsof the grain have a thresholdvoltage determinedby

j

normal transistorequationsfor single-crystalsilicon, but the tr~sistors over the grain "

boundarieshave a much higher thresholdvoltage. A moderategate voltage induces conductingchannelsover the centralregionsof the grains,but barriersstill exist at the grain boundaries.A considerablyhigher gate voltage is therefore required to induce channels over the grain boundaries and form a continuous conducting path. Consequently,the observedthresholdvoltage is higher than expectedfrom the dopant concentrationin the polysilicon grains.Even after a continuousconductingchannelis formed, the transistorcharacteristicsare still limited by the traps at the surface.If the

j

Chapter4: Polycrystalline siliconthin-filmtransistors

78

trap density is high, the chargestatesof many traps needto be changedto increasethe surfacepotentialevenslightly, andthe field-effect mobility is low 1. Becauseof the deleteriouseffect of grain boundaries,large grain size, defectfree polycrystalline silicon is thereforeessentialfor high performancetransistors.As discussedin chapter2, solid phasecrystallization(SPC) of amorphoussilicon (a-Si) is the preferred techniqueto obtain polysilicon films with large grain size and smooth surface 2, and hence better transistor performance.Glass substrates,used in display applications,constrainsthe processingtemperatureof the transistorsto below -650 °c 3. Also for 3-D IC integration,the processtemperatureshouldalsobe kept small so that the preexisting devicesare not affected.However, becauseof this upper limit on the processtemperature,SPC results in long annealtimes 2 (about 20 h or higher), and hencemakesthe processunattractivefor manufacturing.As we discussedin chapters2, severalmethodsof enhancingthis crystallizationprocesshavebeentried, and of these methods, the plasma-induced crystallization potentially introduces the least contaminationto the films. We discussedin chapter3, the effect of an RF hydrogen plasma exposure at room temperatureon the crystallization time of hydrogenated amorphoussilicon films. We found that the plasmatreatmentresultsin the reductionof crystallizationtime by nearly a factor of five comparedto untreatedfilms, and canbe as short as 4 h at 600 °c 4. We also found that the plasmatreatmentcan be maskedto realizepolycrystallineand amorphousregionsin a single silicon layer, and that this can alsoleadto lateral crystallizationfrom the exposedto the unexposedregions. In this chapterwe discussthe performanceof n-channelself-alignedthin-film transistors (TFfs) fabricated in such polysilicon films crystallized from plasmaenhancedchemical vapor deposited (PECVD) a-Si:H after a room-temperatureRF hydrogenplasmatreatment..TFTs with maximum processtemperatureof 600-625 °c

"!C_~y~

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Chapter4: Polycrystallinesilicon thin-film transistors

79

and 1000 °c are compared as function of channel length. The hydrogen plasma treatment is also then locally applied to the source/drain region of the TFfs to seed the lateral crystallization into the channel region. The process leads to larger grains in the channel region and a two-fold increase in the mobility at short channel length to -75 cm2Ns for process temperature of 600 °c. In Section 4.2 the deposition of the precursor a-Si:H, film and subsequent crystallization anneal, and the material properties of the polysilicon film are described. Section 4.3 describes with the high-temperature TFfs, with thermally grown gate oxides. We discuss the low-temperature TFfs next in Section 4.4, with the effect of plasma treatment and anneal conditions on the TFf characteristic, examined in detail. The laterally-seeded TFfs will be discussedin Section 4.5, and we end with a summary in Section 4.6. 4.2 PRECURSOR SILICON FILM DEPOSITION AND CRYSTALLIZA TION The TFfs in this work were all fabricated in polysilicon films, which were first deposited as hydrogenated amorphous silicon (a-Si:H) by PECVD at 150 or 250 °c using pure silane, at pressure of 500 mtorr and RF power density of -0.02 W /cm2, with the thickness of the films being -150 nm (see Appendix A for growth recipes). The substrates were either Coming 1737 or 7059 glass which were pre-annealed as discussed in Section 3.2.1, or silicon wafers coated with -500 nm of SiO2 deposited by PECVD at 250 °c, usingSi~

and N2O, pressure of 400 mtorr and RF power density of

0.1 W/cm2. In all cases,the substrateswere exposed to hydrogen plasma (Section 3.2.1) prior to a-Si:H deposition. In experiments with blanket seeding, the films were then exposed to a room-temperature RF hydrogen or oxygen plasma for one hour in Plasma Therm RIB chamber. Typical plasma conditions were; RF power density of 0.8 W/cm2, pressure of 50 mtorr and flow rate of 50 sccm. The samples were usually placed on a ii;\

1iIt,;""

~3c':'C

Chapter4: Polycrystalline siliconthin-filmtransistors

80

100-125mm Si wafer during exposureto minimize aluminum contaminationof the films as discussedpreviouslyin Section3.4.1.The RIE chamberwas also cleanedprior to loading the samplewith an oxygen plasmaat 0.8 W/cm2 and pressureof 200 mtorr for -10 min to oxidize any trace organic contaminationpresentin the chamberfrom previousruns. Somefilms werenot treatedto plasmaascontrols. After the plasma treatmentthe sampleswere cleanedby rinsing in dilute HF. Annealingat 600 or 625 °C in N2 in a furnace,with the crystallizationmonitoredby UV reflectancemeasurement(Section 3.2.1), then crystallized the samples. The typical grain size for plasma-treatedor untreatedcontrol polycrystallinefilms as observedby TEM is -0.5 ~m (Fig. 3.12 (a». The grains of the completelycrystallizedpolysilicon film are predominantlyorientedin the [111] direction normal to the substratesurface (Fig. 3.11),irrespectiveof prior treatment.

4.3 HIGH-TEMPERATURE TRANSISTORS (:::; 1000 DC) Transistorswere first made using a conventionalself-alignedn-channelhightemperatureprocessflow with a thermally grown gate oxide. Thesedevices are also importantfor usein high-resolutionprojectiondisplays,with poly-Si TFTs usedin pixel switching circuits and in driver circuits, which are fabricated on high-temperature resistantquartzsubstrates. 4.3.1Fabrication details Plasmatreatment and anneal Transistorswere first fabricated after the 600-oCcrystallization anneal by a high-temperatureprocesswith thermally-grown gate oxide. 150 nm of a-Si:H was deposited at substratetemperature(set point) of 150 °c on SiO2 covered silicon substrates.A polysilicon top-gateself-alignedprocesswasthenusedto maken-channel

Chapter4: Polycrystalline siliconthin-filmtransistors

Passivationoxide (250 nm) Alc

Gate

81

n-typepo1y-Si (250 nm)

Drain

1737/7059glassor SiOz/Sisubstrate

Intrinsic poly-Si (150 nm) I

Figure 4.1. Simplified self-alignedTFT crosssectionfor the low-temperatureand high-

temperature process.

I

I

TFTs (Fig. 4.1). The films were either not exposedto a plasmabefore crystallization (anneal time of 20 h) or exposedto a hydrogen plasma (anneal time 4 h) before crystallization.During the plasmatreatment,the sampleswere placedon a large silicon wafer to eliminatethe aluminumcontaminationform the AlzO3electrode4. Deviceisland patterning After crystallization at 600 °c in Nz, device islands were patternedby dry

I

etching with SFdCCizFzplasmaat RF power density of 0.16 W/cmz and pressureof 100mtorr and SF6flow of -25 sccmand CCizFzflow of 1.6 sccmcorrespondingto setpoint of 80 % and 12.5 % on the flow control potentiometers,respectively5. The etch was carried out in PlasmaTechnologyRIB chamber.The etch rate of polysi1iconwas -400 nmlmin. This etch recipe is also quite selectivewith respectto either Sial or glass,the ratio of etch ratesof Si vs. Sial being >30 5. The etching was also monitored by measuringthe interferenceof the reflectedHe-Ne laserbeamfrom the surfacebeing etched as a function of time. This techniqueis useful to detect end-point of etching accurately.

~'c,~

Chapter4: Polycrystalline siliconthin-filmtransistors

82,

Gate Oxidation Before the gate oxidation, the sample was cleaned by rinsing in hydrogen peroxideand sulfuric acid mixture for -10 min, and subsequentrinse in dilute HF. The sampleswere then loadedin the furnace,with Nz flowing in the furnacetube and the furnacetemperatureset to 1000°C. After -5 min (for the sampleto reachthe furnace temperature),the Nz flow was stoppedand Ozflow was started.Oxidation was donefor -20 min andthen the sampleswere annealedin Nz at the sametemperaturefor -20 min. To measurethe thicknessof the oxide, a bare Si lightly doped(-50 .Q.-cm)wafer with (100) orientationwas loadedalong with the polysilicon samples.The thicknessof oxide on the bare Si wafer was easily measuredwith an Ellipsometeror a Nanospec.The thicknessof oxide on the polysilicon film was then estimatedfrom this value, knowing that the polysilicon waspredominantly(111) orientedandthe ratio of oxide thicknessof (111) and (100) orientedsurfacesis -1.75 at 1000°c in the linear regime of growth 6. The thicknessof oxide on the polysilicon sampleswasthen estimatedto be -35 nm. Gate layer deposition, etch and ion implantation The n+ a-Si:Hgate, -250 nm thick, was depositedby PECVD in the p-chamber of the S900plasmadepositionsystemat -300 °c using SiH4,PH3and Hz, at RF power , density of -0.02 W/cmz, and pressureof 500 mtorr (see Appendix A for growth sequence).The gate was then patternedby dry etching in SFdCClzFzplasmawith the plasmaconditionsbeing the sameas thoseusedfor active island etching exceptthe RF power, which was increasedto 0.32 W/cmz. Onceagain laser interferometrywas used for end-pointdetection.The endpointdetectionensuresthat overetchtime is minimized so the damageto gate oxide (exposedto plasmaat the edgesof the gate) is minimal. The gate oxide was then etchedin dilute HF to exposethe source/drainregionsfor ion implantation. Care was taken during this step not to overetchas that would result in

~,c~

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Chapter4: Polycrystalline siliconthin-filmtransistors

83

transistorswith significant gate leakagethrough the thinned gate oxide at the edge of the device. The thicknessof the oxide was also estimatedfrom the surface profile measurement(Dektak) of the samplebefore and after etching the gate oxide. For ion implantationthe small samplepieceswere tapedon a 100-mm8i wafer and were sent out to a vendor.The sourceand drain implant was phosphorusat 60 keV and doseof 2xlO15 cm-2.

Implant anneal and hydrogenation After the ion implantationthe sampleswere annealedat 850 °c in N2 for -30 min to annealthe damage.Onceagainthe sampleswere cleanedby rinsing in hydrogen peroxide and sulfuric acid mixture for -10 min, and subsequentrinse in dilute HF, before loading in the furnace.After the 850-oCanneal,an RF hydrogenationstep was performed to passivatethe grain boundariesin the polysilicon film 7. It has been reportedthat the hydrogenationis most effective at higher substratetemperatureof 300350 °c, due to enhanceddiffusion of hydrogenthroughthe bulk of the film 7. The RF hydrogenationwas done in the i-chamberof the 8900 plasmadeposition system.The PECVD system was chosen, as the RIB chamber (Plasma Therm), wherein the hydrogen or oxygen plasma-seedingtreatments to enhance crystallization were performed,did not haveany heatersto control the substratetemp~rature.The i-chamber was chosen instead of the p-chamber to minimize contamination during the hydrogenationfrom dopants.The n-chamberis usedexclusivelyfor SiNx depositionas mentionedearlier in Section3.2.1. We will discussthe effect of hydrogenationon the characteristicsof the TFTs in the next section. To avoid confusionbetweenthe varioushydrogenplasmatreatmentsusedin this work, henceforth,we will refer all plasmatreatmentsto enhancecrystallization of a-

i'. ,

~""~~

Chapter4: Polycrystalline siliconthin-filmtransistors

84

Si:H films as hydrogen or oxygen plasma seedingtreatment,and hydrogen plasma treatmentto passivatedefectswill be referredto ashydrogenation. In some cases,a 250-nm thick passivationoxide was depositedby PECVD at 250 °c after the hydrogenationstep in the plasmadepositionsystem(PlasmaTherm) using 35 sccm of Si~ and 160 sccm N20 at RF power density of OJ W/cm2 and pressureof 400 mtorr. Etching in bufferedHF openedcontactholes. Finally aluminummetal was thermally evaporatedon the samplesand patterned to form gate, source and drain contacts(Fig. 4.1). To ensuregood electrical ohmic contactbetweenthe Al layer and the Si film, the samplewas rinsed in very dilute HF before the metal depositionto removeany native oxide at the surface.However, care must be taken so that the gate oxide is not etched.The contactswere then annealedin forming gas (mixture of 10% H2 in NV at -250 °c for -90 s in AGA associatesrapid thermalannealer.The schematiccross-sectionof the final deviceis shownin Fig. 4.1. No significant differencesin the characteristicsof the transistorswere observed by including the passivation oxide step in the processflow. The drawback is the increasein the numberof processsteps(1 additionalmask).On the other hand,this step increasesthe lifetime of the transistoras the gate oxide (near the edges)is no longer exposedto the atmosphere(Fig. 4.1), andthereis no dangerof etchingthe gateoxide as earlier,asthe gateregion is maskedduring the contacthole definition step. The hydrogenationcould also be done after the metal step, but we chosethis sequenceof stepsfor two reasons.The primary concernwas to minimize the antenna effect during the hydrogenation.The antennaeffect occurswhen large me,talareasover either the field-oxide in caseof regular ICs in bulk Si, or over the underlying glassor SiO2in caseof ICs in SOl layers, act as chargecollectors8. This collectedchargeis

.

then appliedon the gateof the transistor.The currentstressthroughthe small areawith

"'4'~

Chapter4: Polycrystallinesilicon thin-film transistors

85

the gate oxide is therefore increased by the antenna ratio which is the area of the metal connected to the gate divided by the area of the transistor (see Section 7.2 for more details). The second reason is that the i-chamber can no longer be used for hydrogenation after the metal step (to avoid contamination of the chamber) and therefore the hydrogenation has to be done in the p-chamber, increasing the chance of contamination (p-chamber is where doped films are grown). The transistors were then tested on a Hewlett Packard 4l55A ParameterAnalyzer. 4.3.2 Results and discussion For all the TFTs discussed in this chapter, the field-effect mobility

was

calculated from the maximum value of the transconductance (dIos/dVos) at Vos

= 0.1

V. The effective channel length was used in the calculation, which was derived from difference between the drawn channel length and the x-intercept of the straight line fit to l/los vs. drawn channel length for fixed [V os - VTH]. As the threshold voltage (Vrn) can vary with channel length, the value of Vos was varied for the different channel length transistors such that the [V os - Vrn] is fixed. The straight-line fit assumed a constant mobility and was done for L>5 ~m, since for short L an increase in mobility was observed. The threshold voltage was deduced from the x-intercept of the straight line fit to Ios vs. Vos for Vos =0.1 V.IoFF is the minimum value ofIos when Vos =5 V, and ioN is the maximum value of Ios when Vos

= 5 V and Vos is scanned from -10

to

20V. Effect of RF hydrogenation During the hydrogenation, the hydrogen plasma etches a-Si:H but not poly-Si,

hencecompletecrystallizationof the n+ a-Si:H gate layer must be ensuredbefore loading the samples for the hydrogenation step. Significant etching and sputtering of the a-Si:H deposited on the walls of the chamber or on the sample holder occurs during the

, ~".

Chapter4: Polycrystalline siliconthin-film transistors

86

hydrogenationstep, and this a-Si:H is depositedon the transistorsamples.To prevent this unwanteddeposition,the chamberwas first cleanedwith a hydrogenplasmaunder the sameconditionsfor -20 min prior to loadingthe samples. Addition of argon(-50 %) is known to increasethe ionization efficiency of the plasma and thereby increasethe hydrogen ion density 9. But this led to significant etching of poly-Si too during the plasma treatment.So in our work we used pure hydrogenplasmato passivatethe defectsin the polysilicon films. The chamberpressure during hydrogenationwas high (1 torr) aswe could not strikeplasmaat lower pressures. Higher pressureleadsto higherdensityof hydrogenions andradicalstherebyimproving the hydrogenationefficiency. The hydrogenationcondition (RF power density and exposure time) was then optimized to realize maximum field-effect mobility and minimum leakage current (Figs. 4.2 (a) and (b)). The field-effect mobility of the transistorsincreasedas the RF power density during hydrogenationwas raised (Fig. 4.2(a)). Higher RF power densitiesleadsto increasedhydrogenion density and larger number of hydrogen atoms in the plasma and hence better defect passivation.The ON/OFF current ratio of the TFTs also increasedfor longer hydrogenation.The ON current increasesas the number of defect states,which act as carrier scatteringsites decreases. The leakagecurrentdecreasesasthe numberof defect statesin the band-gap , that act as generationsites contributing to source/drainjunction leakage,decreases. However, prolonged exposureto hydrogen plasma led to decreasein the ON/OFF currentratio (Fig. 4.2(b)). This is primarily due to increasein leakagecurrents,the ON currents in fact increasedslightly. The increasein leakagecurrent might be due to increasingdamageduring the plasmaexposurefrom the UV photonsand the surface charging(from the ions and electronsflux) leadingto degradationof the gatedielectric 1°.We will discussthe plasma-induceddamagemechanismsandthe techniquesto

~)!!',"fI"".,_" -"

Chapter4: Polycrystallinesilicon thin-film transistors

87

100 Hydrogenation 300°C,1 Torr,50 sccm,60 min

W N< 80 E .9....E:-

:g

60

E U 2 "ij5

40

:Q Q)

iL 20 0.0

0.1

0.2

0.3

0.4

0.5

0.6

RF power density (W /cm2) (a) 108

~

W /L=54 !1m/10 !1m tox-40 nm

~

107 0 "-='

-~

106

U

105

[:: Q) ''~

u.

u. 0

~

104

Hydrogenation RF power 0.6 W/cm2,

103 0

20

40 60 80 100 Hydrogenation time (min) (b)

120

Figure 4.2. Effect of hydrogenation on the high-temperature TFf characteristics, (a) field-effect mobility of the TFfs as a function of the RF power during hydrogenation, and (b) ON/OFF current ratio of the TFfs as a function of exposure time during hydrogenation.

~

Chapter4: Polycrystalline siliconthin-filmtransistors

detenninethe damagein more detail later in Chapter7. The optimum conditions in terms of field-effect mobility and leakage current were found to be substrate temperature(set point) of 350 °c, RF power density of 0.6 W/cm2,pressureof 1 torr, hydrogenflow of 50 sccm,andexposuretime of 60 min. Effect of hydrogen-plasma-seedingtreatment Fig. 4.3 showstypical TFT characteristicsafter optimum hydrogenation,which were similar and well behavedfor devicesin films both with andwithout the hydrogenplasma-seedingtreatment,with no significantdifferencebetweentwo kinds of devices. The thresholdvoltage was -0.1 V, the subthresholdslope was -0.5 V/decadeand the ON/OFF current ratio was in excessof 107,for both the control and the hydrogen-

I

plasma-treated samples.

i

Within experimentalerror, the control andhydrogen-plasma-seeded sampleshad similar linear region field-effect mobilities. They were -75 cm2Ns at long channel length,but rose up to -100 cm2Ns at channellength of -2 ~m (Fig. 4.4). Othershave observedan increasein mobility at short channellengthsin polysilicon TFTs 11,12.It has been attributed to grain sizes on the order of a channel length, leading to large portion of the channel with no grain boundariesobstructingthe motion of electrons ,

from the sourceto the drain. Thus our resultsimply a grain size of few microns, much larger than the as-crystallizedfilm. The apparentincreasein grain size over that after the 600-oCcrystallization, might result from a grain ripening effect during the hightemperatureoxidation and the ion implantationannealsteps,during which the grains

orientedin the minimumenergyconfigurationgrowat the expenseof others13. Hightemperatureprocessingmight alsoresult in the annealingof the structuraldefectswithin )

the grains

I,

r

--, ~!.,

88

~'7~ I

Chapter4: Polycrystalline siliconthin-filmtransistors

89

10.2

W/L=56I1m/1111m 10-3 tox-35 nm

V Ds=5V

10.4

V Ds=0.1 V

--- 10.5

~

"E 10.6 Q) '-

~

10.7

C .~ 0

10.8

10

-9

10-10

.

control,withoutH2plasma

0

H2 plasma exposed

10-11 -4

-2

0

2

4

6

8

Gate voltage (V) (a)

1.4

Hydrogenplasma-treatedsample 1.2 -;;r:

VGs=5.1 V

W /L= 56 I1m/11 11m t ox -35 nm

1.0

g

VGs=4.1V

"E 0.8 Q) ''-

~

0.6

VGs=3.1V

c:

~

0

0.4

VGs=2.1V

0.2

V -

0.0 0

2

4

6

8

Drain voltage (V) (b)

Figure 4.3. (a) Drain current vs. gate voltage characteristics, and (b) drain current vs. drain voltage of high-temperature poly-Si TFfs made of films annealed at 600°C with and without H2 plasma-seeding treatment prior to anneal with thermal oxide grown at 1000 °c. Anneal times at 600 °c is 4 h for H2-plasma-treated sample and -20 h for untreated sample.

~

"

Chapter4: Polycrystallinesilicon thin-film transistors

110

"'"

00100 N< 90

"p

E

~

/

~

::0

70

~

:t:

-8-

°2 plasmatreatment

~ - ~-::::=:--.1 A-

£"'~-o

High temperature TFTs 60 Low temperature TFTs

50

tox=150 nm, PECVD at 350°C

Q) I

~

no treatment H2 plasma treatment

Thermal gate oxide (35 nm)

80 PECVDoxlde (130 nm)

+-'

-8-.A.-

",

.".?: o E

90

40

Q)

iL

30 2

4

6

Effective

8 channel

10 length

12

14

16

(~m)

Figure 4.4. Field-effect mobility of high-temperature TFrs as a function of channel length, for untreated (with thermal oxide and PECVD oxide) and plasma-treated (blanket-seeded) films. Field-effect mobility of samples 5, 6 and 7 (Table 4.1) fabricated with low-temperature PECVD oxide also shown for comparison.

of the polysilicon 14, or else some grain boundaries are electrically inactive after the high-temperature anneal, leading to improved performance of the TFrs. 4.4 LOW-TEMPERATURE TRANSISTORS (~ 600 DC) 4.4.1 Fabrication details Low-temperature TFrs were made in polycrystalline films on glass substrates not exposed to a plasma before crystallization (anneal time of 13 or 20 h depending on the growth temperature of the initial a-Si:H films), and in films exposed to an oxygen (typical anneal time 7 h) or hydrogen (typical anneal time 4 h) plasma before crystallization, with all crystallization done at 600 °c 15. Table 1 lists the different process conditions for different samples. After the crystallization, n-channel TFTs were fabricated by a standard self-aligned top-gate process, similar to that for the high-

~--

-

Chapter4: Polycrystallinesilicon thin-film transistors

91

temperature TFfs, except for the low process temperature. After the films were completely crystallized at 600 °c, the active area was defined by dry etching as described in Section 4.3.1. Gate oxide deposition Next -150 nm gate oxide was deposited by PECVD in the Plasma Therm RF plasma deposition chamber. The sample was rinsed in dilute HF to remove any native oxide on the polysilicon surface prior to the deposition. The PECVD chamber was first cleaned with a CF4 plasma (0.8 W/cm2, 200 mtorr) for -15 min. After the etching step, a thin -100 nm of SiNx was then deposited to minimize flakes (etch residue) from the chamber walls depositing on the sample during the normal gate oxide deposition. After these chamber-preparation steps, the samples were loaded in the chamber on a 100 mm Si wafer (for uniformity of oxide deposition), and Si02 was deposited on them. The conditions during Si02 deposition were substrate temperature (set point) of 350 °c or 250 °c, flow of 35 sccm of SiH4, and 160 sccm of N20, pressure of 400 mtorr, and RF power of 0.1 W Icm2. The gate oxide was then annealed for -2 h in O2 at 600 °c in some cases. A few samples had gate oxide deposited by magnetron PECVD at 250 °c at Lawrence Livermore National Laboratory, courtesy of Dr. Steven Theiss. About 250 nm a-Si:H layer doped in-situ with phosphorus (-1020 cm-3) was deposited by PECVD in the p-chamber of the multi-chamber S900 system at -300 °c using 44 sccm of Si~, 6 sccm of PH3 and at a chamber pressure of 500 mtorr and RF power of -0.02 W/cm2 to form the gate (see Appendix A for details). Phosphorus doping in the a-Si:H films increasesthe crystallization time as discussed previously in Section 3.3.6. Therefore we tried increasing.the deposition temperature of the n+ a-Si:H gate layer to -350 °c to reduce the crystallization time. But this led to significant peeling of the layer during deposition itself. A substrate temperature of -300 °c was

~.'""~'

1j;)'!,t!I1r"

Chapter4: Polycrystalline siliconthin-filmtransistors

92

found to be good trade-off. After the gate was patternedby dry etching in SF6 and CChFz plasma (RF power -0.3 W/cmz, pressureof 100 mtorr) the source and drain were implanted with phosphorusat 50 keY and a doseof 2x1015cm-z.The annealof implant damage in the source/drain and crystallization of the gate was done simultaneouslyby annealingat 600 °c in Nz for -6 h, with the rate limiting stepbeing the complete crystallization of the gate. As discussedpreviously in Section 4.3.1, completecrystallizationof the gateis essentialso that the gateis not etchedduring the subsequenthydrogenationstep.Note that the maximum processtemperatureis limited to 600 °C. An RF hydrogenationstepwas performedto passivatethe grain boundaries in the polysilicon film as in the case of the high-temperatureTFT~ at substrate temperature(set point) of 350 °c, RF power density of 0.6 W/cmz, pressureof 1 torr, hydrogenflow of 50 sccm,and exposuretime of 60 min. (section4.3.1). A passivation250-nmthick SiOz was depositedin somecasesby PECVD as describedpreviously in Section4.3.1. Etching in bufferedHF openedcontactholes. Finally aluminumcontacts were evaporatedand patterned and the metal contacts were annealedas before in forming gas at 250 °c for 90 s in the RTA chamber.All I-V data were measuredas beforeon the HP 4155A ParameterAnalyzer. 4.4.2Resultsand discussion Well-behavedcharacteristicswere obtained in all casesas can be seen from Table 4.1. Typical characteristicsof drain currentvs. gatevoltage and vs. drain voltage are shown in Figs. 4.5(a) and 4.5(b) respectively,for a device in a film treatedwith a hydrogen plasma before a 4-h 600-oCcrystallization step (sample 7 in Table 4.1). Typical resultsare mobilities in the rangeof 30-40 cmzNs, subthresholdslopesfrom 1 to 2 V/decade,and ON/OFF currentratios from 105to 106.In the subsequentsections, the effectsof annealingtime andplasmatreatment,the effect of the channellength,the

,

I

~

Chapter4: Polycrystalline siliconthin-filmtransistors

S. No

1 2 3 4 5 6 7 8 9 10 11

a-Si:H growth

Plasmapretreatment

temp (OC)

Type

150 150 150 150 250 250 250 250 250 250 150

On Si wafer

Annealat 600 °c (h) Cryst. time

Gateoxide

Imp. ann.

Temp (OC)

Anneal in O2

Standarddeviationof the data 20 6 250 No H2 Yes 4 6 250 No H2 Yes 20 6 250 No 20 45 250 No 12 6 350 Yes 02 No 8 6 350 Yes H2 No 5 6 350 Yes 12 6 250 No H2 Yes 5 6 250 No H2 Yes 8 6 250 No 20 6 Livermore ox.

93

"

TFf characteristics(Leff- 3.5 ~m) ~linear (cm2Ns)

VTH

(V)

S!oNf!oFF (V/dec)

:!: 1.5 :!:0.3 :!:0.2 38 0.8 1.6 33 -7.5 1.7 33 0.8 1.4 37 -6 2.4 42 0.2 2.6 38 3.4 1.4 35 3.2 1.6 30 0.1 2.0 24 -7 1.8 24 -0.8 1.6 32 -4.5 2.5

2x 10° 10° 106 106 2x105 4x105 7x10' 3x10' 5x105 5x10' 105

Table 4.1. Processconditions and TFf results for devices fabricated with blanket plasmatreatment,with maximumprocesstemperatureof 600 °C. Except for devices3, 4 and 10, the crystallizationtimes are the minimum requiredto saturatethe changein UV reflectance(measureof degreeof crystallization).

, .

1

Chapter4: Polycrystallinesilicon thin-film transistors

94 ,

10-3 W=55I!m, L=3.5 I!m 10-4 t ox=150 nm -5

10

~

Control,untreated

'"

10-6

=0.1 V

+-'

c:

~ 10-7 ::J

U c: 10-8 o@ '-

0

10-9

0

H2 plasma treated

0

°2 plasma treated

10-10 10-11 -15

-10

-5

0

5

10

15

20

Gate voltage (V) (a) 175

W/L=55 /lml6.5/lm 150 tax=150 nm H2 plasma treated -125 « ~ ---

"E 100

VGS=12.1 V

Q) ''-

~

75

oS

V =10.1 V

~ 50

I

GS

!

0

25 I

I

0 0

2

4 6 8 Drainvoltage (V)

10

12

(b)

Figure4.5. (a) Drain currentvs. gatevoltage,and (b) drain currentvs. drain voltagefor TFfs in polysilicon films with andwithout plasmatreatmentprior to anneal.(samples 5,6 and 7 in Table 4.1).

95

Chapter4: Polycrystallinesilicon thin-film transistors

50

-

45

E

40

cn ::e

'-,

::a

-

"'-

! !

0

~

..:: ()

Q)

~

:t= W

25

'-- '-

-,

---

~ ---"---:I:

.T I

20

t

I '

::t-

150 nm a-Si at 2500 C

.(

1--

15 1

2

3

4

5

6

7

8

9

10

11

Channel length (11m)

Figure 4.8. Field-effect mobility of polysilicon TFfs in hydrogen-plasma-treated films annealedfor varioustimes at 600 °c as a function of channellength.For a-Si:H growth temperatureof 150°C and250 °c, samples1 and 8, respectively. boundariesin the channel.Thereforewe expectlarger field-effect mobility for the TFTs with polysilicon films from a-Si:H depositedat lower temperatures.A similar trend was seen for the hydrogen-plasma-seeded samples(Fig. 4.8), in which the field-effect mobility reduced to -25 cm2Ns from -33 cm2Ns for channel length of 3.5 ~m (samples2 and 9, Table 4.1) when the growth temperaturewas raised from 150 °c to 250 °C. There was no significant change in threshold voltage in either case. The hydrogenplasmatreatmentis moreefficient in creatingseednuclei in films depositedat lower temperature4: the crystallizationtime at 600 °c was reducedto -4 h from -5 h when the growth temperaturewas lowered to 150 °c from 250 °c (as we discussedin Section3.3.4). But it is not clear why the field-effect mobility of the hydrogen-plasma-

Tlc."lr_T"',ri"'I

.J

Chapter4: Polycrystalline siliconthin-filmtransistors

101

treatedTFfs shoulddecreaseasthe growth temperatureof the precursora-Si:H films is raised. Effect of gate oxide and high-temperature anneal after crystallization The gate oxide plays an importantrole in determiningthe TFfs characteristics. Nearly all the TFfs fabricatedin this sectionusedPECVD gateoxide. The temperature of depositionof the PECVD oxide also affectsthe propertiesof the oxide and therefore the characteristicsof the TFfs. The field-effect mobility of the TFfs increasedfrom -30 cm2Ns to -42 cm2Ns for the control samples(samples8 and 5, Table 4.1), and from -24 cm2Ns to -35 cm2Ns for the hydrogen-plasma-treated samples(samples9 and 7, Table 4.1), when the depositiontemperatureof the PECVD oxide was changed from 250 °C to 350 °c, and a 2-h 600-oC anneal in O2 was added after the gate deposition.Thesearethe highestmobilities found in both the control and the hydrogenplasma-treatedcases.The thresholdvoltage of the TFfs increasedslightly from 0.1 V to 0.2 V (samples8 and 5, Table 4.1) when the gate oxide growth temperaturewas increasedto 350 °c andannealedin 02 subsequently. The PECVD gateoxide hasa high fixed chargedensity of -1012cm-2and a high interface-statedensity -1012cm-2eV-1, as deducedfrom C-V measurementof MOS capacitorson crystalline Si substratesmade using the samegateoxide. Subsequentannealof the oxide at 600 °c in O2did not affect the interface-statedensitiesappreciably,though the fixed positive chargedensity was slightly reducedfrom -6x1011cm-2to -3x1011cm-2after -2 h of anneal,which might explain the small increasein thresholdvoltage of the n-channelTFfs with the gate + oxide annealin 02. The TFf performancewith gateoxide depositedby magnetronplasma-enhanced CVD at Lawrence Livermore National Laboratory by Dr. Steven Theiss was also examined.The field-effect mobility of an untreatedcontrol samplewith a magnetron-

Chapter4: Polycrystalline siliconthin-filmtransistors

102

PECVD oxide depositedat 250 °C was -32 cm2Ns (sample11,Table 4.1) as compared to -38 cm2Ns for the control sample(sample1, Table 4.1) with normal PECVD oxide at L=3.5 ~m. The subthresholdslope of the TFfs with magnetron-PECVDoxide was -2.5 V/decadeas comparedto -1.6 V/decadefor the TFfs with the regular-PECVD oxide. The lower mobility and poorer subthresholdslopein caseof the TFfs with the magnetron-PECVDoxide suggeststhat the interface-statedensity is higher for the gate oxide deposited by magnetron-PECVD.The threshold voltage of the magnetronPECVD devicewas -4.5 V comparedto 0.8 V for the normal PECVD device at L=3.5 ~m. The large negativethresholdin the former casemight be due to the higher fixed oxide charge,which is typically positive,in the magnetron-PECVDoxide. As discussedpreviously, the higher value of mobility in case,of the high"-

temperatureprocesscomparedto the low-temperaturecase,might be due to the increase in grain size 13andlower numberof defectstateswithin the grain 14,and/orreductionin interface-statedensity for the dry thermaloxide. To find out the dominanteffect, TFfs were made in polysilicon films annealedat 1000 °c after the 600 °c crystallization anneal with PECVD gate oxide, and comparedwith TFfs with thermal gate oxide grown at 1000°c. The field-effect mobility of the transistorswith PECVD oxide and a high-temperatureannealwas -75 cm2Ns vs. -82 cm2Ns for the TFfs with thermal gate oxide at long channel lengths. The field-effect mobility also shows similar dependenceon channellength in both cases,indicating increasedgrain size of a few micronsdue to the high-temperatureanneal(Fig. 4.4). The subthresholdslope,which is proportional to gate oxide thickness when the sum of polysilicon space-charge capacitanceand the interface-statecapacitanceis much greater than the gate oxide capacitance,is -1.8 V/decadefor the 130nm PECVD oxide vs. 0.5 V/decadefor the 35 nm thermal oxide. But the ON/OFF current ratio (106vs. 10l is poorer in caseof the

, - -

i

Chapter4: Polycrystallinesilicon thin-film transistors

103

PECVD gate oxide TFfs due to higher leakage current. This data clearly indicates that mobility of high-temperature TFf is predominantly affected by the high-temperature anneal leading to increased grain size, and not by the gate oxide quality. The thermal oxide with the lower interface-state density results in lower leakage currents compared to the PECVD oxide and only marginal improvement in field-effect mobility. This leads us to the conclusion that overall TFf performance can be improved with large-grain polysilicon and higher-quality gate oxides like thermal oxide or ECR oxide 2°. Non-self-aligned n-channel TFfs fabricated in polysilicon films crystallized after an ECR oxygen plasma treatment at 400 °c, with a maximum process temperature of 600 °c, have also been reported 21.The process details were, however, not reported. The TFfs had a field-effect mobility of 35 cm2Ns and ON/OFF current ratio of -106, which are similar to the values in this work. 4.5 LATERALLY-SEEDED LOW-TEMPERATURE TRANSISTORS 4.5.1 Device Concept In the previous section we found that the field-effect mobility

of high-

l

temperature long-channel (>10 ~m) TFfs is -75 cm2Ns, compared to -35 cm2Ns for the low-temperature long channel TFfs. The field-effect mobilities of theses transistors are primarily limited by the grain size, due to scattering of carriers at the grain boundaries. Our aim is to increase the mobility

in polycrystalline silicon low-

temperature (~ 600 °C) transistors by increasing grain sizes, within a reasonablethermal budget. If the grain boundary locations can be controlled, transistors can then be fabricated within a grain, eliminating the grain boundary effect altogether. A large grain size can be achieved by a very high-temperature anneal (-1000 °C), after the polysilicon is first formed, so that the large grains grow at the expense of

I

-

Chapter4: Polycrystallinesilicon thin-film transistors

1;

104

H2plasma

Nucle"

111111 +

-

S . I

O2

"

.-.'

(a)

Anneal at

-600 °c Crystalgrowth

,

/

n+ a-Si

from seed Si02

1

y-

po

n

,

dueto lateral growth from S & D region

.

S

+ I

Large grain in channel

Anneal at -600°C

I

(b)

T

"

op VIew

(c)

Figure 4.9. Schematic cross-sectionof the laterally hydrogen-plasma-seeded TFT fabrication sequence.(a) Hydrogen plasma seedingin source/drainand gate regions after ion implantation and gate/deviceisland definition steps.(b) Crystallization and implant damageannealat -600 °C. (c) Cross-sectionalview and top view of device after completecrystallization.

-

-

Chapter4: Polycrystalline siliconthin-filmtransistors

105

the small leading to an overall increasein grain sizes 13and mobility in the 1000-oC processvs. the 600-oCprocess(discussedin detail in Section6.2.4). An alternativeis the lateral grain growth of polysilicon from the source and drain regions into the adjacenta-Si:H channelregionto directly form large-grainpolysilicon in the channelat 600 °C. This processhas the added advantagethat the grain boundary location is controlled, i.e. for the right channel length, the number of grain boundariesin the channelcan be reducedto just one at the center of the channel (dual seeding).This techniqueinvolves selectiveseedingby hydrogenplasmatreatmentof the sourceand drain regionsmaskedby the gateasillustratedin Fig. 4.9. To eliminatethe single grain boundaryat the centerof the channel,seedinghasto be doneonly at the one end (either drain or source).This, however,leads to increasedmasks and aligning steps,as the seedingwill now haveto be doneearlierandthe transistorfabricatedsubsequently,such that the channelis in the laterally crystallizedregion 12. Note, other groupshave donesimilar lateral crystallizationusing metalslike Ni 22,

or germanium12,leading to either Ni or Ge contaminationin the channelregions,

respectively. Patternedlight absorptionmasks were also used to fabricate laterally crystallized polysilicon TFTs 11, but this techniquerequirestransparentsubstratesand the crystallizationannealwasdoneat high-temperatureof 850 °c. We will discussthese techniquesin further detail in chapter6. 4.5.2 Selectivecrystallization Selectivecrystallization with plasmaseedingcan be done by masking against the plasma with an oxide 21,23.As discussedin Section 3.3.7, 100 nm of SiO2 was depositedby electron-beamevaporationon top of 150 nm of a"Si:H film depositedat 150°c. The SiO2wasthenpatternedandthe sampleswereexposedto hydrogenplasma. Then all the remainingSiO2was strippedand the sampleswere annealedin the furnace

-

~"

Chapter4: Polycrystalline siliconthin-filmtransistors

106

for -4 h at 600 °C. The exposedareascrystallizedcompletely as expected,while the unexposedareasremain amorphous4. The amorphous/polycrystalline differenceof the two regionswas also confirmedby UV reflectancemeasurements. Note that the size of the crystalline area increaseswith time. This shows that the crystalline/amorphous interface front moves out of the seededareasto the unexposedareas,with the lateral crystalline growth rate being -0.5 /.lm/hr at 600 °c 4. The lack of crystalline grain nucleationin the unexposedarea,which is a result of the higher activation energy for nucleationthan the activation energyof crystal growth, leadsto larger silicon grains in the lateral growth areathan in the plasma-seeded areas.This was confirmed by planview transmissionelectronmicroscopy(TEM) measurements of the films, which shows that the lateral grain growth from seededregionsresults in grains as large as -3 /.lm (Fig. 3.12 (b)). The grains in the seededregionsthemselves,as in caseof the blanket crystallization, are only -0.5 /.lm in size (Fig. 3.12 (a)). The TEM samplepreparation involved chemically etching a hole in the substrateto realize an electron-transparent film at the edge of the hole (see Section 3.2.3 for further details on TEM sample preparation). 4.5.3 Fabrication of laterally-seededtransistors We used the hydrogen-plasmaseedingtechniqueto fabricate laterally-seeded TFTs with higher mobility. The source/drainregionswereusedasthe seededregionsto promote lateral crystal growth in the channel.No additional lithography steps were required becausethe patternedgate was used as the mask for the hydrogen plasma seedingtreatmentas illustrated in Fig. 4.9. The transistorswere fabricatedusing a 150 nm a-Si:H layer depositedat a substratetemperatureof 150°C. The activeislandswere then patternedby dry etching in SFdCCbFz plasma as describedearlier. The gate

.

-'-~-

Chapter4: Polycrystalline siliconthin-filmtransistors

107

I

insulator usedwas PECVD Sia2 depositedat a substratetemperatureof 250 °C. Note that the gateoxide is depositedon a-Si:H andthe crystallizationannealis donewith the \ ..

gateoxide coveringthe channelregions.This is in contrastto the low-temperatureTFTs discussedin Section4.4.1 where,the gateoxide was depositedafter the amorphousfilm wascompletelycrystallized. A 250-nm thick phosphorus-dopeda-Si:H film was then grown for the gate (see

AppendixA for growthrecipe).After patterningthe gate,the sampleswereimplanted

1

with phosphorusto form the source and drain contacts.A few sampleswere then exposedto hydrogenplasma(seeded)to createseednuclei in the exposedsourceand drain and gate electrode regions and annealedat 600 °c and 625 °c along with unseededcontrol samples.Both the crystallization and the implant annealwere done simultaneously.The annealtime of -20 h at 600 °c and -6 h at 625 °c was chosensuch that the channelregion of the longestchannel(-15 ~m) TFTs and the n+ a-Si:H gate layer was completelycrystallized,consideringthe crystal growth velocity is -0.5 ~m/h at 600 °c 4 andthat phosphorus-doped source/drainregionsand gatetake longer time to

crystallize24. The hydrogenplasmaseedingreducedthe crystallizationtime for the crystallizationof the phosphorus-doped gate4. Transistorswere also fabricatedwith the lateral crystallizationannealof the channeldoneprior to the ion implantationstep.This involved two 600-oCsteps,one to crystallize the channel and:anotherto anneal the implant damage,and thereforea higher thermal budget. RF hydrogenationwas done after the crystallization/implant-damage annealas in case of the low and hightemperatureTFTs discussedpreviously. The back-endprocessingwas the samewith passivationoxide deposition,etchingcontactholes,depositionof aluminum,patterning contactsand annealingthe contactin forming gas, all done as previously describedin Section4.3.2.

-

'i

Chapter4: Polycrystalline siliconthin-filmtransistors

S.

a-Si:H

No.

growth temp (OC)

12 13 14 15 16 17 18 19 20 21 22

150 150 150 150 150 150 150 150 250 250 150

Plasmapretreatment Seed After ion implant

PECVD Gate

Anneal

Oxide N2O Magnet plasma ron

temp (OC)/ time (h)

Standard deviation of data Yes Yes No No Yes No Yes Yes No No Yes No Yes Yes No Yes Yes No Yes No No No No No Yes Yes Yes No Yes Yes Yes Yes Yes

No No No No Yes Yes No No No No No

600/20 600/20 625/5 625/5 600/20 600/60 600/25 600/25 600/12 600/12 600/20

108

TFf characteristics (Leff 2 J.Lm)

-

!t1inear Vrn (cm2Ns) (V)

i: 3 72 37 68 30 50 48 44 32 28 27 74

i: 0.5 -4 -4 -4 -4 2.4 2.3 -5 -5 -2 -1.5 -2.5

S (VI dec)

IoNI IOFF

i: 0.2 1.6 1.7 1.6 1.7 1.5 1.6 2.0 2.4 2.6 2.6 2.3

2x 107 2x106 107 3x106 3x106 106 4x106 8x10' 104 104 104

i ..

Table 2. Laterally-seededlow-temperatureTFf characteristicsfor various growth, annealand processconditions.The column, "after ion implantation" ref~rs to whether the H2 seedingtreatmentand lateral crystallization,was donebefore or after the S & D ion implantation step. The column, "N2O plasma" refers to whether the gate PECVD oxide wastreatedto N2Oplasmaafter deposition.Seetext for further details.

Chapter4: Polycrystallinesilicon thin-film transistors

109

4.5.4 Results and discussion Table 4.2 lists the characteristics of the laterally-seeded TFfs under various process conditions, with the measurement conditions being the same as those mentioned in

,

Section 4.4.2. The laterally-seeded transistor (sample 12) showed excellent characteristics as can be seen in Fig. 4.10 with ON/OFF current ratios of -107 and subthreshold slopes of about 1.7 V /decade. The threshold voltages of the TFfs decreases as the channel length is reduced because of the short-channel effect as discussed previously, with the threshold voltage of both the unseeded and seededTFfs equal to -4 V at L

- 2~m (Fig. 4.11(a)). The threshold voltages are more negative

compared to the low-temperature TFfs discussed in Section 4.4.2, with the shift in

-

thresholdvoltagebeing -2 V. The negative shift in the threshold voltage in case of the unseeded or seeded TFfs fabricated in this manner might be due to the long anneal at 600 °c after implantation. Long anneal times were necessary in this case as the crystallization of the amorphous active layer and the implant damage anneal were done simultaneously. We saw similar large negative threshold voltages in case of the lowtemperature TFfs that were annealed for long duration after the ion implantation step (sample 4, Table 4.1). The large negative threshold could also be due to the higher fixed charge density in the PECVD oxide, as in this case the oxide was deposited on the aSi:H layer prior to the crystallization anneal in contrast to after the crystallization anneal for the low-temperature TFfs discussedpreviously in Section 4.4. The dopant diffusion during the long anneal (-20 h at 600 °C) could lead to shorter effective channel length and therefore result in an apparent increase in fieldeffect mobility as deduced from the drawn channel length. Therefore the effective channel length was calculated by plotting l/IDs as a function ,"of the drawn channel length for various IVos - V THIvalues and finding the x -intercept of the straight line

~

Chapter 4: Polycrystalline silicon thin-film transistors

110

10-2 10-3 10-4

~

10-5

a5

10-6

~

10-7

V d =0.1 V S

+-'

''-

Blanket crystallization

8

.S

: ~=37 cm2/Vs

~ 10-

0

10-9 10-10 10-11 -20

-15

-10

-5 0 Gate voltage

5 (V)

10

15

20

(a) 11

Gate voltage of seeded TFTs W/L=54 ~m/2"3 ~m tsio,-130 nm

10 9 ;;r:

8

g c

7

~

6

G

5

c: "(ij

4

'-

0

Anneal at 600 °c

. 0

Blanket crystallized, control

Laterally seeded

3 2 1 0

0

2

4

6

8

10

12

14

Drain voltage (V) (b)

Figure 4.10. (a) Drain current vs. gate voltage, and (b) drain current vs. drain voltage of the seeded and un seeded control poly-Si TFTs (sample 12 and 13) with maximum processing temperature of 600 °C.

Chapter4: Polycrystalline siliconthin-filmtransistors

111

(Figs. 4.12(a) and 4.12(b)) with VTHcalculatedfor each channellength (as discussed previously in Section 4.3.2). For fixed values of field-effect mobility, 1/IDs varies linearly with channel length and in ideal situation it goes to zero when the channel length goesto zero. Hence,the x-interceptis & and Leffective = Ldrawn - &. But as the field-effect mobility is not expectedto be constantfor all the channellengths in this case, the straight line fit is limited to Ldrawn > 5 ~m and extrapolatedto yield the effective channellength. The & valuesare nearly the same(0.2-0.4 ~m) for both the seededandthe unseededTFTs. The mobility of the transistorfor different channellengthsis shownin Fig. 4.11 (b). At long channellengths,the field-effect mobilities of the laterally-seededTFTs are

- 37 cm2Ns, slightly higherthan in the unseededprocess.Not known if significant.At short channellengths,< 5 ~m, the control devicesshow negligible changein mobility, but the laterally-seededdevicesshow a large increasein mobility up to -72 cm2Ns. This is attributedto the larger grain size in the channelregion of the laterally-seeded transistor.The negligible changein mobility as channellength is reducedin the control devicesmeansthat the effective grain size is much smaller than the smallestchannel length (2 ~m) asseenin Section4.4.2. The leakagecurrent (minimum drain current in the OFF state)of the laterallyseededTFTs is -3 pN~m comparedto -35 pN~m for the unseededcontrol devices. The large grainsin caseof the laterally-seededdevicesmeansfewer grain boundariesin the channel region and hence fewer number of trap states,leading to lower leakage current.This dependence of leakagecurrentof polysilicon TFTs on the grain size of the polysilicon hasalsobeenreportedelsewhere25.

~-

112

Chapter4: Polycrystallinesilicon thin-film transistors

a-Si:H at 150°C

-.

-2

>

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f f

hr anneal at 600°C t20=130 nm; W=54 11m

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2

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Effective channel length (~m) (b)

Figure 4.11. (a) Threshold voltage calculated from the x-intercept of the straight line fit to drain current vs. gate voltage at Vos = 0.1V for different channel lengths in seeded and unseeded TFTs. (b) Field-effect mobility calculated at Vos=O.l V as;a function of effective channel length in the seededand unseededTFTs.

j l

~

i ;

Chapter4: Polycrystallinesilicon thin-film transistors

113

6

2.0x10

Anneal

- 20

at 600°C

H2 plasma

h

seeding

6

1.5x10 -~

'«

-CJ)

1.0x1 0

-"0

6

~

5.0x105

0.0

0

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Channel

6

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8

10

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(~m)

(a)

I

2.5x106 Anneal at 600°C - 20 h Control, unseeded 2.0x106

--

~

~

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1.5x10

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1 .Ox1 06

5

5.0x10

0.0

~

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2

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Channel

6

8

length

10

12

(~m)

(b)

Figure 4.12. Plot of 1/IDsas a function drawn channel length for various values of IVGSVTH I to extract the effective channel length for (a) the laterally-seeded TFfs, and (b) unseeded,control TFfs. Note the straight line is fitted for the longer channel lengths as the method implicitly assumesfixed field-effect mobility, and VTHis calculated for each channel length.

.

Chapter4: Polycrystalline siliconthin-filmtransistors

114

In the subsequentsection,the effects of crystallizationannealtemperatureand length of anneal, effect of lateral crystallization done before or after the ion implantationstep,effect of the growth temperatureof the precursora-Si:H film, and the effect of N2Oplasmatreatmentof the gateoxide will be studied.The processconditions to realizeoptimum laterally-seededtransistorperformancewill thenbecomeclear. Effect of annealing temperature and time We studiedthe effect of annealingtemperature(samples14 and 15 vs. 12 and 13, Table 4.2) on the grain size and hence on the electron mobility. The annealing temperaturewas changedto 625 °c, from the 600 °c usedin the previousexperiments. We found that the time taken to crystallizeuntreatedfilms was reducedfrom -20 h to -5 h and the lateral crystal growth rate was enhanced.However,the mobility became 1 smaller in the control samples(sample 15 vs. sample 13), probably becauseof an increasein nucleationdensity at higher annealtemperature,leadingto smaller grains 2. Fig. 4.13 shows the linear field-effect mobilities in the seededand the unseeded transistors(samples14 and 15) samplewith the crystallizationtemperatureof 625°C. The mobility in the control sampleis -25 cm2Ns when annealedat 625 °c, compared to -35 cm2Ns when annealedat 600°Cat L>5 ~m. But the seededTFTs havenearly the samemobility irrespectiveof the annealingtemperature.The advantageof using higher temperature (625°C vs. 600°C) is that the annealing time is reduced but the disadvantageis that one has to use more expensive glass substrates,(for display applications)with higher strainpoint temperatures 3. A few of the sampleswere also annealedfor longer times up to 60 h at 600 °c (sample17, Table 4.2). Thesesampleshad gateoxide depositedby magnetronPECVD at 250 °c. The longer annealdid not result in any significantchangein any of the TFTs characteristics,in fact the..mobilityof the TFTs reducedslightly to -48 cm2Ns

-

Chapter4: Polycrystalline siliconthin-filmtransistors

-U> '::> ",'-

115

70

a-Si:H deposited at 150°C

60

5 h anneal at 625 °c t ox-130nm;W=54~m

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""'"

10 2.5

2.6

2.7

2.8

2.9 1 OOOIT

3.0

3.1

3.2

3.3

(1 /K)

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contrast to the as-grown a-Si:H film deposited at 150 °c, which had a considerable SiH2

content (Fig. 5.2). The Tauc optical gaps (Eopu calculated from the optical

transmission spectra above the band-gap show that the Eoptdrops to 1.6 eV from 1.8 eV during annealing and that rehydrogenation raises Eopt to 1.7 eV (Fig. 5.4). Dark conductivity (ad) measurement shows that ad of the a-Si:H film increases after the anneal and that ad has a low thermal activation energies, indicating conduction through defect states (Fig. 5.5). Rehydrogenation brings the activation en'ergy of the film closer to Eg/2 indicating a reduced defect density. But ad still is not as small as that of the asgrown a-Si:H and suggestsconduction in a heterogeneousmaterial, which may explain the slightly higher leakage currents of the transistors (Fig. 5.14). Overall, the data show that the capped a-Si:H film remains largely amorphous after the anneal, and that rehydrogenation results in a-Si:H film which may be suitable for devices.

Chapter5: Integrated amorphous andpolycrystalline silicontransistors

134 ,

5.4 TRANSISTORPERFORMANCEAND OPllMIZATION 5.4.1 Fabrication details Non-self-aligned n-channel top-gate transistors were fabricated in both the amorphousand polycrystalline silicon regions.Fig. 5.6 showsthe processsequenceof the transistorfabrication.A 120-nmthick SiNx was depositedby PECVD at 200 °c (set point) as describedearlier in Section5.2.1,on a 150-nmthick a-Si:H layer depositedat 150 °c on Coming 1737glasssubstrate.After patterningof the SiNx by etching with dilute HF (1:10 deionized water), the samplewas then exposedto the RF hydrogen plasma in the RIE system as describedearlier. Subsequentannealingwas done in a furnace at a temperatureof 600°C in a N2 ambient with the SiNx cap selecteda-Si regions.After -4 h of annealthe region exposedto hydrogenplasmawas completely crystallized, while the unexposedareasremain amorphous.The remaining SiNx mask layer was then removedby etching in dilute HF, leaving behind both amorphousand polycrystallinesilicon in a singlesilicon layer. Rehydrogenationof the film is essentialto improve the TFT performanceas discussedearlier. This was doneby exposingthe sampleto hydrogenplasmaat the RF power of 0.2 W/cm2at substratetemperatureof 350 °c (setpoint) andpressureof 1 torr for -75 min asdiscussedin Section5.3. Details on the rehydrogenationand its effect on the amorphoussilicon TFf characteristicswill be discussedsubsequently. After the rehydrogenation

': step, -50 nm of n+ microcrystalline (~c-Si:H) silicon

was deposited by PECVD (in the p-chamber of the S900 multi-chamber PECVD system)using Si~, H2 and PH3,at a pressureof 900 mtorr, RF power of -0.3 W/cm2, and at a substratetemperatureof 340 °c

18 (Fig. 5.6 (a)), seeAppendix A

for the growth

recipe.Device islandswere thendefinedby dry etchingin a SF6andCCl2F2plasmaat ~,

Chapter5: Integrated amorphous andpolycrystalline silicontransistors

135

50nm

n+ ~c-Si:H ...

1737glass

1737glass

a) Re-hydrogenate and

b) Define activeislandsfirst,

(usuallywithout breaking vacuumin between)

dry etching

depositn+ ~c-Si:H

followedby S&D regions,by

AI

1737glass

c) Depositgatedielectricof 130-180nm SiO2

1737glass

d) Opencontactholesand depositmetal for gateand S&D

Figure 5.6. Amorphousand polycrystalline silicon top-gatenon-self-alignedtransistor fabrication steps. The steps after the selective crystallization;step are shown. The processrequired four masksfor the TFT fabrication and an additional mask to define the polycrystallineandamorphousregions.

.

-

Chapter5: Integrated amorphous andpolycrystalline silicontransistors S

G

D

S

SiOz

G

136 D

SiOz

~c-

1737glasssubstrate a) Non-coplanarSID contacts resultingin source/drain;resistance

1737glasssubstrate b) Overetchingduring channel definition leadingto increased source/drainresistance

Figure 5.7. Exaggeratedcross-sectionof the a-Si:Wpoly-Si TFT showingthe (a) effect of non-coplanarsource/draincontacts on source/drainresistance,and (b) effect of overetchduring channeldefinition on source/drainresistance. an RF power of -0.3 W/cmz and pressureof 100 mtorr (similar to the etch recipe used to etch device islandsin the self-alignedTFT processdiscussedin Section4.3.2). The future channel regions were defined by dry etching just the n+ ~c-Si:H layer in a separateetching stepusing a CClzFzand Oz plasmaat an RF power of 0.08 W/cmz and pressureof 100 mtorr with CClzFzflow rate of 9 sccmand Oz flow rate of 5 sccm(Fig. 5.6 (b)). The n+ ~c-Si:H and device-islandetching were both done in the Plasma TechnologyRIE chamber. During the etchingstep,laserinterferometry(seeSection4.3.1) is usedto detect endpoint and accuratelydeterminethe thicknessof the layer etched.But during the channel-definitionstep,the layer (n+~c-Si) thicknessto be etchedis only -50 nm and we needto stop when the intrinsic layer is reached.The laser interferometrytechnique is powerful when the layer to be etchedis silicon on an insulator,so that endpointcan

Chapter5: Integrated amorphous andpolycrystalline silicontransistors

137

be detectedonce the signal is flat with no interferencefringes. The techniqueis also helpful if the Si layer to be etchedis at least80-nmthick, asthe differencebetweentwo

=

maxima or minima (!JJ.d ')J2n) corresponds to Si thickness of -80 nm for He-Ne laser.

,

Due to thesereasons,the samplecan get overetchedduring the channel-definitionstep resulting in damage at the channel surface and therefore increased source/drain resistance(Fig. 5.7). Somevariationsin the processsequencewere tried to minimize this etching damageof the channelas discussedlater in Section5.4.2. The samplewas then rinsed first with sulfuric acid and hydrogen peroxide solution and then dilute hydrofluoric (HF) acid to cleanthe surface.This also helpsin smootheningthe surface as rinsing in sulfuric acid peroxide mixture results in a thin oxide (-5 nm) which is subsequentlyetchedduring the HF rinse. The oxide also gettersany impurities (like ,

metals) from the samplesurfaceand hencereducesthe amountof contaminantsat the channelsurface. The gatedielectric, 130-180nm of SiNxor SiO2,was then depositedby PECVD at a substratetemperatureof about 250 °c (Fig. 5.6(c)). Care was taken to changethe recipes such that all processingafter rehydrogenationwas done at lower temperature than the rehydrogenationtemperatureso that no loss of hydrogenagain occursduring the subsequentprocessing.The SiO2 was depositedin the plasma deposition system (PlasmaTherm) with the depositionconditionsandthe chamberpreparationstepsbeing that sameas that describedpreviouslyin Section4.4.1 to fabricatethe low-temperature self-alignedTFTs. The SiNxwas depositedin the n-chamberof the S900multi-chamber PECVD system(see Appendix A for growth sequence).The growth temperaturewas 300 °c with a Si~ flow of 13 sccm,NH3 flow of 130 sccm,and H2 flow of 143 sccm. The chamber pressurewas 500 mtorr and the RF power density was -0.02 W/cm2 during the SiNx deposition. The typical growth temperatureof SiNx used as gate

~

Chapter5: Integrated amorphous andpolycrystalline silicontransistors

138

dielectric for a-Si:H TFfs is -350 °C 1,19.The depositiontemperaturewas lowered in this case to ensure that no loss of hydrogen occurs due to processing done at temperaturehigher than or equal to the rehydrogenationtemperature:Due to the lowered growth temperaturethe quality of the nitride films degradesdu~ to increased porosity leading to poor electrical characteristicslike gate leakage and breakdown voltage 2°. Hydrogen (50 %) was addedduring growth to improve the quality of the nitride layer 2°. Contact holes were then made to the sourceand drain regions by etching in dilute HF and aluminumwas evaporatedandpatternedto form the gate,and sourceand drain contacts(Fig. 5.6(d)). The sampleswere then annealedat -225 °c in forming gas (10% H2 in Nv for -90 s in AGA associatesrapid thermal annealer(RTA) to reduce contactresistance.Note this is not a self-alignedprocess.The processis similar to the inverted-staggered processtypically usedfor a-Si:H TFfs in activematrix liquid crystal displays. 5.4.2 Techniquesto minimize channel-etch damage The transistorfabricationprocessdescribedaboveinvolves a channel-definition stepduring which the deposited-50 nm of n+~c-Si is etchedto define the source/drain regions. Due to the inherent limitations of the laser interferometry as discussed

,

previously overetching occurs and the etch leads to damageat the channel surface which is detrimentalto both amorphousandpolycrystallinetransistorperformance.The overetchalsoleadsto increasedsourceanddrain resistanceascanbe seenfrom Fig. 5.9 and thereby degradesthe performanceof the TFfs, especiallythe polysilicon TFfs. Variations in the processflow were thereforetried to reducethis channel-etchdamage asdescribednext.

Chapter5: Integrated amorphous andpolycrystalline silicontransistors

He-Ne laser

139

Laserinterferometry to detectendpoint resist n+~c-Si

1737glasssubstrate Etchingof n+ ~c-Si with laser interferometryto detectendpoint. Figure 5.8. Schematiccross-sectionof sampleduring channeldefinition etch of n+~c-Si with the n+~c-Si depositedafter the activeislands(a-Si:H/poly-Si)werepatterned.

n+ ~c-Si after active island patterning The only changein this processcomparedto the regular processdescribed earlier in Section 5.4.1, is that in this casethe active islands were patternedafter the rehydrogenationstepbeforethe n+ ~c-Si depositionstepas seenin Fig. 5.8. During the channel-definitionstepinvolving the etch of n+ ~c-Si, laser interferometrycan be used to accuratelydeterminethe end of etching (as the etch involves Si on insulator). This ensuresthat overetch and etch-relateddamageis minimized. Care should be taken, however,to cleanthe samplewith dilute HF prior to the n+ ~c-Si depositionto ensure good electrical contactbetweenthe activelayer and the n+ ~c-Si layer. This was not so crucial in the standardprocessasthe n+~c-Si wasdepositeddirectly on the unpatterned active film after the rehydrogenationstepwithout breakingvacuum.This variation still involves exposureof the channelsurfaceto the plasmaduring the etching, but better endpoint detectionensuresreduceddamageand a more repeatableand hencea robust process. The effect on the TFT characteristicsis primarily the reduction of the

Chapter5: Integrated amorphous andpolycrystalline silicontransistors

140

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~""""""""""""""" ~ ~

It")

00 It")

N

-

It")

- 00

g. ~

e ~

~

'-'

'""'

U

U~

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,;';~'""'

t/).~ ~ ,~

:I:-5. e ~5b~~

,;';~Q. t/)o

rn ~

E-;p-p-

-~

Chapter5: Integratedamorphousandpolycrystallinesilicon transistors

IDS = ,ueffCoxW [VDs(VGs -VTH)] L

144

(5.1)

With contact resistance of RD and Rs at the drain and source ends, and assuming a symmetric device with RD

= Rs, equation (5.1) can be rewritten

as (ignoring second

order terms) IDs~

kVds(VGS-VTH)

(5.2)

1 + 2kRs(VGS -VTH) + kRSVDs

where k = J.leftCox W/L and Rs is the contact resistanceat the source/drain. Equation (5.2) can be used to perform a least square fit of the data and the values of k, Vrn and Rs can be extracted for one device of one channel length. For polysilicon TFfs, Rs was found

-

to be as high as 300 k.Q in some casesfor channel width of 200 ~m, which means that equation (5.1) would have resulted in a pessimistic estimate of J.leff.Table 5.1 lists the values of field-effect mobility for the poly-Si TFfs calculated from equation (5.2) under the column titled "No Rs", and from the maximum value of the transconductanceunder the column titled "With Rs", showing the effect of source/drain resistance on the extracted field-effect mobilities. For the a-Si:H TFfs, on the other hand, the effect of the source/drain resistance was negligible as the channel conductance and mobilities are much lower than for the poly-Si TFfs. 1) Deposition temperature The a-Si:H TFfs fabricated in this fashion show greatly improved performance when the a-Si:H films are deposited at 150 °c instead of 250 °c, as can be seen for samples 1 and 2 in Table 5.1 and in Fig. 5.10. The crystallization time of hydrogenplasma-treated a-Si:H films at 600 °c reduces from 5 h to 4 h for a reduction of a-Si:H deposition temperature from 250 °c to 150 °c as we discussedearlier in Section 3.3.4.

Chapter5: Integrated amorphous andpolycrystalline silicontransistors

10.5 10

-6

145

W /L=200Itm/50Itm, Samples

1 and 2

10.7 10.8

i:H deposited at 1

':;i;:

::[;: ~

~

.-24 h with !

the SiNx cap on vs. crystallization time of 15-20 h without the SiNx-cap layer). The SiNx has larger bond lengths than the a-Si:H and is deposited at higher temperature than the a-Si:H film (200 vs. 150 °C). This results in tensile stress in the thin a-Si:H films which inhibits nucleation during the subsequentcrystallization anneal 24-26.This would ensure that the regions covered by the nitride remain amorphous and lose comparatively less amount of hydrogen during the high temperature annealing. All samples shown in Table 5.1 had SiNx-cap layer on the amorphous regions during the selective crystallization anneal. "'"

Chapter5: Integrated amorphous andpolycrystalline silicontransistors

, :

148

4) Temperature of annealing Another processparameter,which can be changedeasily, is the crystallization temperature.The a-Si:H TFTs mobility increasedto 0.7 cm2Ns from 0.5 cm2Ns for samples6 and 7, respectively,without changein IoFFwhen the crystallization anneal temperaturewasincreasedto 625 °c from 600 °c. In fact, the highertemperatureanneal led to better performancea-Si:H TFTs with field-effect mobility as high as 1.2 cm2Ns (Figs. 5.13 (a) and (b)) when the rehydrogenationtime wasincreasedto 75 min from 60 min for sample 12. As we discussedin Section 3.3.2, increasing the annealing temperatureby 25 °c from 600 °c resultedin reductionof crystallization time of the hydrogen-plasma-treated region by nearly a factor of 4 from -4 h to -1 h. The reduced crystallization time during selectivecrystallizationmight lead to lower hydrogenloss from the amorphousregions.However,the crystallizationtime of the hydrogen-plasmatreatedregion hasan activationenergyof about2.7 eV 6, and the diffusion of hydrogen from the a-Si:H films, which is also a thermally-activatedprocess,has an activation energyof 1.6 to 2.8 eV 22,23.This would meanthat in addition to fastercrystallization rates at higher temperatures,the hydrogen effusion rate is also enhancedat higher temperatures.But, due to the slightly lower activationenergiesof the hydrogeneffusion process,the amountof hydrogenlost during the 1-h 625-oCannealmight be less than that lost during the 4-h 600-oCanneal.This might explain the higher a-Si:H field-effect mobilities observedin caseof the highertemperatureannealprocess. On the other hand,the field-effect mobilities of the poly-Si TFTs decreasedby a factor of nearly two from 14 cm2Ns to 8 cm2Ns for samples6 and 7, respectively,as the temperatureof anneal was increasedfrom 600 to 625 °c. As the annealing temperatureis raisedthe grain size in the polycrystallineregionsis reducedbecausethe highernucleationrate leadsto closelypackedgrains27, which would explain the

i

Chapter5: Integrated amorphous andpolycrystalline silicontransistors

149

12 anneal 625 °c 10 re-hyd: 45 W, 75 min tSiO2=130nm 8 W/L=210~m/30~m

.-

«

--::i

6

(/) "0

4 2

VGs=9 V V Gs=6V

0

0

2

4

6

8

10

12

14

Vds (V) (a) 10-4 -5 anneal 625 °c 10 re-hyd : 45 W, 75 min

Vds=10 V

10-6 tSiO=130 nm -7

10

.-

« --

w/L=210/lm/30/lm

V =0.1 V ds

10-8

(/) -"0

10-9

10-10

.

10-11

:. -

10-12

10-13

0

5

10

15

20

V95 (V) (b)

Figure 5.11. Best a-Si:H TFr characteristicsfor crystallization annealat 625 °c and rehydrogenationat 0.2 W/cm2for 75 min, (a) linear characteristics,and (b) subthreshold characteristics.

"'"'~,~

Chapter5: Integratedamorphousandpolycrystallinesilicon transistors

150

smaller mobilities for the poly-Si TFfs annealed at higher temperature. A similar reduction in mobility with increase in annealing temperature was also seen in case of self-aligned polysilicon TFfs discussed previously in Section 4.5.3. Optimization of both poly-Si and a-Si:H TFfs will require more experiments with time-temperature programs for the crystallization anneal. S) Rehydrogenation condition Though SiNK is used as a cap layer during the crystallization process, extensive f I j

hydrogen outdiffusion does occur (Section 5.3). The TFfs fabricated in a-Si directly after the crystallization anneal, without any rehydrogenation (sample 8), have poor mobilities of -0.02 cm2Ns, while the poly-Si TFfs have mobilities of -7 cm2Ns. Rehydrogenation is therefore required to passivate the dangling bonds in the amorphous region

and thereby improve

the electrical

characteristics of

the film.

But

rehydrogenation is a double-edged sword, as the hydrogen radicals abstract hydrogen from the a-Si:H layer and even etch the amorphous silicon layer by inserting themselves in Si-Si bonds and creating volatile Si~

28, 29.

Therefore, the hydrogen plasma

parameters,primarily the RF power and exposure time, have to be adjustedjust right, so that the film

is sufficiently

hydrogenated but not etched. This requires that

rehydrogenation be done at low RF power and high pressure to reduce the hydrogen ion energy, and that the substrate temperature be raised to acceleratethe hydrogen diffusion into the bulk of the film. The optimum condition was found to be a hydrogen plasma at RF power density of 0.2 W/cm2, chamber pressure of 1 torr, H2 flow of 50 sccm, substrate temperature of 350 °c and exposure time of -75 min. The effect of rehydrogenation on the materials properties of the annealed a-Si:H films has been discussedpreviously in Section 5.3.

'c ~d

_.,-"

Chapter5: Integratedamorphousandpolycrystallinesilicon transistors

151

In addition to setting the plasma conditions right so that etching of the a-Si:H is minimized, the chamber walls and the electrodes should also be prepared prior to the rehydrogenation step. As discussedin Section 4.3.2, hydrogena~ionfor grain boundary passivation of the poly-Si TFTs requires that the chamber be prepared by striking a hydrogen plasma prior to loading the samples to remove any a-Si:H on the chamber I

walls or on the electrodes to minimize any a-Si:H deposition on the samples. However, in this case we had to deposit a-Si:H on dummy glass slides using the same sample holder as the one used for the actual rehydrogenation, to coat the chamber walls and the sample holder with a-Si:H film. This was done to minimize etching of the a-Si:H film during the subsequent rehydrogenation step. During the rehydrogenation step, the aSi:H film deposited on the walls and the electrode is also etched, and thereby the etching of a-Si:H film on the sample substrate is minimal. This dummy coat of a-Si:H must be done at low temperatures (-150 °C), as the etch rate of a-Si:H in hydrogen plasma increases if the growth temperature of the film is lowered and this ensures that the dummy a-Si:H film is preferentially etched. The etching effect of the hydrogen plasma was most severe when the rehydrogenation was done after the active islands were patterned, which reduces the effective area of the a-Si film to be hydrogenated (reduced loading factor). Also, the previous history (runs) of the sample holder and the deposition chamber plays an important role. It was found that the etching of a-Si:H during rehydrogenation was minimized if the a-Si:H was deposited in the previous runs as compared to nitride or ~c-Si:H films. Coating the sample holder prior to the actual rehydrogenation with -300 nm of a-Si:H deposited at 150 °c minimizes this dependenceon the previous history of the chamber and the substrate/sampleholder. All this goes to prove that the rehydrogenation step is a very critical step and the most

--

.'

152

Chapter 5: Integrated amorphous and polycrystalline silicon transistors

:'0.4

~

a-Si:H TFTs after 600°C anneal Gate dielectric is SiNx 0.3

Re-hydrogenation: 60 min, 350°C

(\J

E

--()

>-

+-' .~ 0

i I

0.2

~ +-' ()

I

'+-

"Q) 0.1 I

"0

iL

0.0 0.0

0.1

0.2

0.3

0.4

RF Power Density (W/cm2)

(a) 1.0 a-Si:H TFTs after 600°C anneal Gate dielectric is SiO2 (\J~

;

E

~

106

0.8 Re-hydrogenation:0.2 W/cm2,35 C

5

0.6

10

.==

u.. u.

.c 0

-0

E 0.4

)

+-'

-

~

104

Il)

-6 0.2 ~ i:i:

0.0

103 0

10

20

30

40

50

Re-hydrogenation

60

70

80

90 100

time (min)

(b) Figure 5.12. Field effect mobility of the a-Si:H transistors for different rehydrogenation conditions, (a) as a function of RF power (samples 8,4,2 and 9), and (b) as a function of exposure time (samples 10,7, 11 and 13). I

/" :

153

Chapter5: Integratedamorphousandpolycrystallinesilicon transistors

-4

~ 0

-

~ I:: Q)

C

0 U I:: Q) 0> 0

2

'-

"'0 >..t::

~

150 nm a-Si deposited

at 150 DC

Anneal at 600 DC for 4 h Rehydrogenate:

RF power 0.2 W/cm2

0 0

20

40

60

80

100

Rehydrogenation time (min)

Figure 5.13. Net hydrogencontentas estimatedfrom the integratedIR absorptionnear 630 cm-l in the a-Si:H films after rehydrogenationfor various exposuretimes. The hydrogenplasmaconditionswere: RF power density of 0.2 W/cm2,pressureof 1 torr, and hydrogenflow rate of 50 sccm.The growth temperatureof the initial a-Si:H film was 150°c, depositedon SiO2iSisubstratefor infrared absorptionmeasurement. demanding.SeeAppendix A for the actualrehydrogenationprocesssequencewith the recipesfor the dummya-Si:H film andthe rehydrogenationstep. Fig. 5.12(a) shows the effect of RF power (samples8, 3, 2 and 9) and Fig. 5.12(b) illustratesthe effect of plasmaexposuretime (samples10, 7, 11 and 13) on Jln and IoN/IoFFof the a-Si:H TFTs, respectively.Increasingthe rehydrogenationtime beyond 75 min led to significant etching of the a-Si:H film. When the exposuretime was increasedto 90 min from 75 min, the hydrogencontentof the film fell (Fig. 5.13) from 4.4 at. % to -3 at. % (as measuredby IR absorption at 630 cm-l) with a correspondingdecreasein field-effect mobility of the a-Si:H TFTs (Fig. 5.12(b)). High RF power densities(>0.2 W/cm2)led to etchingin spiteof all the chamberpreparations

_c'

Chapter5: Integrated amorphous andpolycrystalline silicontransistors

154

asdiscussedearlier, and above0.4 W/cm2the a-Si:H film wascompletelyetched.When the RF power was too low, the hydrogenationwas not efficient, leading to poor fieldeffect mobility for the a-Si:H TFfs. The poly-Si TFf characteristics,on the other hand,were essentiallyunchanged, asrehydrogenationwas not a critical stepfor them.Any changeobservedin the poly-Si performancewhen only the RF hydrogen conditions were changed (e.g. between samples6 and 10, Table 5.1) probably is due to a variation in the percentageof crystallinity of the film after the 4-h annealat 600 °c, andnot relatedto hydrogenation. This is in contrastto the effect of hydrogenationon the field-effect mobility observed earlier in caseof the self-alignedpolysilicon TFfs in chapter4. This might be because the rehydrogenationwas done at far lower RF power densities(-0.2 W/cm2)during the integrated TFf

processing (to minimize the a-Si:H film etching as discussed

previously) comparedto the RF power density (-0.6 W/cm2)during hydrogenationfor defectpassivationfor self-alignedpoly-Si TFfs. In fact the improvementin field-effect mobility of the self-alignedpoly-Si TFfs was minimal at low RF power densities,and significant improvementonly occurredat RF power densitiesof 0.4 W/cm2 or larger (Fig. 4.2). Another reasonmight be that the field-effect mobility of carriers in caseof the non-self-alignedpoly-Si TFfs is limited by carrier scatteringat the poly-Si/SiO2 interface,as the channelis etchedduring processing,ratherthan by carrier scatteringat the grain boundaries.And since,hydrogenationdoesnot reducethe surfaceroughness of the films, the field-effect mobility of the non-self-alignedpoly-Si TFfs is not changeddue to hydrogenation. 6) Gate dielectric Traditionally a-Si:H TFfs havebeenfabricatedwith bottom gatesand SiNx gate dielectricto obtain the lowestinterface-statedensity.This led to improved~n and higher

-

_J

i

Chapter5: Integratedamorphousandpolycrystallinesilicon transistors

155

IoN/IOFF19.But poly-Si TFfs are fabricated usually with top gates and SiO2 as the gate

dielectric 3°. Hence a trade-off is required.We comparedSiNKand SiO2 as the gate dielectric in the top gate configuration for both the a-Si:H and the poly-Si TFfs. With SiO2 as the gate dielectric, deposited at 250 °c by PECVD, from SiH4 and N20, and at RF power density of -0.1 W/cm2, the poly-Si TFfs had ~n of -14 cm2Ns (sample 11). On the other hand, TFfs with SiNK as the gate dielectric, deposited at 300 °c by PECVD, using Si~, H2 and NH3, and at a RF power of -0.09 W /cm2 had ~n of -9 cm2Ns (sample 2). Although the SiO2/a-Si:H interface-state densities are higher than that of the SiNx/a-Si:H interface 31,the leakage currents were not significantly increased when SiO2 was used as the gate dielectric instead of SiNK for the a-Si:H TFfs. But, the ioN and hence ~n were also higher (0.5-1 cm2Ns compared to -0.2 cm2Ns), with IoFF of only -10-50 fA/~m when SiO2 was the gate dielectric instead of SiNK, Therefore, overall best results for both a-Si:H and poly-Si TFfs were obtained with SiO2 as the gate dielectric. 7) Post metal hydrogenation All the transistors were annealed in forming gas (10% H2 in NV at -225 °C as mentioned earlier in Section 5.4.1 to reduce the contact resistance between the n+ ~cSi:H source and drain layers and the aluminum prior to I-V measurement.In addition to this anneal, a further hydrogenation using a RF hydrogen plasma at RF power of 0.6 W /cm2 and exposure time of 60 min substrate temperature of 250 °c and pressure of 1 torr (similar to the conditions used for hydrogenation of self-aligned poly-Si TFfs discussed in Section 4.3.1) reduced IoFFfrom -250 fA/~m to -30 fA/~m for the a-Si:H TFfs (Fig. 5.14). But there was no change in ~n of either the poly-Si or the a-Si:H TFfs (sample 2, Table 5.1). However, this step did not lead to such drastic reduction in IoFF

Chapter5: Integrated amorphous andpolycrystalline silicontransistors

156

10-4

10

-5

10-6

-«

~0

-

a-Si:H deposited at 150°C W /L=200~m/50~m tSiN,-170 nm

10-7 10-8 10-9

10-10

10

Post Metal hydrogenation

-11

10-12

10-13 -10

0 -5

0.6 W/cm2, 250°C 60min, 1 Torr

-':J

. .

.0

teTFTs

0

5

10

15

20

V GS (V)

Figure 5.14. Drain current as a function of gate voltage plotted on log scaleof a-Si:H TFfs before and after post-metalhydrogenation,showingthe reductionin IoFF, while ioNremainthe samefor sample2, Table 5.1. of sample 11, which was rehydrogenated after the 600-oC anneal step under the

!

! optimized conditions as discussed previously, and therefore did not require any

subsequenthydrogenation.The implication is that the post-metalhydrogenationstepis essentialonly if the prior rehydrogenationwas incomplete,i.e., not all the dangling bondsin the a-Si:H layer werepassivated. Overall optimization The best performanceof a-Si:H TFTs in this processflow was achievedwhen the selectivecrystallizationannealwas doneat 625 °c insteadof the usual 600 °C. This processyielded a-Si:H TFTs with field-effect mobilities as high as 1.2 cm2Ns with ON/OFF current ratio> 106,subthresholdslopeof 0.4 V/decadeand thresholdvoltage of -6 V. However, the field-effect mobility of the poly-Si TFTs was lowered to -9 cm2Ns comparedto -14 cm2Ns for the poly-Si TFTs with the 600-oCcrystallization anneal(sample12,Table 5.1).

Chapter5: Integratedamorphousandpolycrysta1linesilicon transistors

157

The best performancefor the non-self-alignedpoly-Si TFfs was achievedfor the processwith 600-oCcrystallizationannealwith SiO2as the gatedielectric and with the n+ ~c-Si:H depositedafter the device islands have been patterned(to minimize overetchingof the channel as discussedin 5.4.2). The field-effect mobility of these poly-Si TFfs was -14 cm2Ns and the ON/currentratio was >105 (sample 11, Table 5.1). With the self-aligned processflow discussedin chapter 4, for the hydrogenplasma-treatedpoly-Si TFfs, higher field-effect mobility (-33 cm2Ns) and better ON/OFF currentratios (-106) canbe achieved(sample2, Table 4.1). With the laterallyseededprocessflow, the performancecould be improvedeven further to achievefieldeffect mobility ashigh as75 cm2Ns and ON/OFFcurrentratio greaterthan 107(sample 12, Table 4.2). The self-alignedprocess,however,requiresan additional 6-h 600-oCprocessstepto annealthe source/drainimplant damage(Section4.4.1). This results in more complicated processingas the amorphousregions would have to be covered during this anneal to minimize loss of hydrogen, in addition to requiring another rehydrogenationstep. Higher numberof high-temperaturestepsleads to the increased degradationof a-Si:H TFf characteristics. To achieveoptimum performancefor both poly-Si and a-Si:H TFfs with the sameprocessflow, severaltrade-offswere requiredlike, 600-oCannealinsteadof 625°C anneal,SiO2 insteadof SiNx as the gate dielectric, and the use of non-self-aligned processwith depositedn+ ~c-Si:H for source/draincontacts instead of self-aligned process with ion-implanted source/draincontacts. The optimum conditions for the fabricationof the integratedpoly-Si anda-Si:H TFfs after selectivecrystallizationby

';'

"..'

.I

Chapter 5: Integrated amorphous and polycrystalline silicon transistors

158

Integrated a-Si and poly-Si TFTs on 1737 glass

10.4 10.5 10.6

-

10-7 10.8

~

~ _°

10-9

-

10.10

a-Si:H top gate TFTs

10-11

W /L=200Ilm/50Ilm

10-12 10-13 -10

-5

0

5

10

15

20

V GS (V)

Figure 5.15. Drain currentas a function of gatevoltageplotted on a logarithmic scaleof optimizeda-Si:H and poly-Si TFfs madeof the samea-Si:H precursorfilm on Corning 1737glasssubstrate(sample11). Poly-Si is obtainedby the selectivecrystallizationof hydrogen-plasma-seeded a-Si:H at 600 °c in N2for 4 h. annealingat 600°C are those given for sample 11 in Table 5.1. The ~n in the linear regime were -0.7 and 15 cm2Ns for the a-Si:H and poly-Si TFfs, respectively,with SiO2as the gate dielectric. IoFFof a-Si:H TFf is -10 fA/~m and ioN of the poly-Si TFf is -l~A/~m, with IoN/IoFF of both typesof devices~105(Fig. 5.15). Theseresults compare favorably with work on integrating a-Si:H and poly-Si TFfs by laser processing,which resultedin a-Si TFfs with ~n of -0.9 cm2Ns and poly,Si TFfs with ...

~n of -20 cm2Ns 4. These a-Si:H TFfs also comparefavorably with conventional

inverted-staggered TFfs, whichhave~nof-1 cm2NsandIoNIIoFF-1071,19. A typical result for top-gatea-Si:H TFf with SiNxasthe gatedielectric,is field-effect mobility of -0.4 cm2Ns and ON/OFF currentratio of -105 32.Our resultsfor a-Si:H top gateTFfs after a 600 or 625 °c annealingsteparethe bestreported.

Chapter5: Integrated amorphous andpolycrystalline silicontransistors

159

5.5 SUMMARY A maskedexposureto a RF hydrogenplasmacanbe usedto spatiallycontrol the subsequentcrystallization of a-Si:H to poly-Si, resulting in polycrystalline silicon and amorphoussilicon areason the samesubstrate.The selectivecrystallization effect has beenusedto fabricateTFTs in both the poly-Si and a-Si:H regionsin a single layer of silicon for the first time with no laserprocessing.All the transistorfabrication stepsfor both a-Si:H and poly-Si were sharedso as to minimize cost. The only additional mask requiredwas to createthe amorphousand polycrystallineregionsin the single Si layer. Careful control of the rehydrogenationprocessachievedhigh field-effect mobility in the amorphous silicon after the 600-0C-crystallizationprocess. Optimized transistor fabrication producedgood TFr characteristicsfor both the poly-Si and a-Si:H TFTs. The poly-Si TFrs had an electron mobility of -15 cm2Ns and the a-Si TFr had an electronmobility -0.7 cm2Ns. In both casesthe ON/OFF current ratio was >105.This techniquecan thereforebe usedto integratea-Si:H TFT for pixel switching and poly-Si TFrs for row/columndriver circuits in active-matrixliquid-crystaldisplays.

Chapter5: Integratedamorphousandpolycrystallinesilicon transistors

160

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,

,;

\ ,!

C'4""""_~

Chapter5: Integratedamorphousandpolycrystallinesilicon transistors

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[23]

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[25]

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161

'

Y. Z. Wang,S. J. Fonash,O. O. Awadelkarim,and T. Gu, "Crystallization ofa-Si:H on glass for active layers in thin film transistors:Effect of glass coating," Journal of ElectrochemicalSociety,vol. 146,pp. 299-305,1999. C. V. Thompson,"Grain growth in polycrystallinesilicon films," Materials Research SocietySymposiumProceedings,vol. 106,pp. 115-125,1988. E. Srinivasan and G. N. Parsons,"Hydrogen elimination and phase transitions in pulsed-gasplasma depositionof amorphousand microcrystallinesilicon," Journal of Applied Physics,vol. 81,pp. 2847-2855,1997. E. Srinivasan, H. Yang, and G. N. Parsons,"Ab initio calculation of hydrogen abstractionenergeticsfrom silicon hydrides," Journal of ChemicalPhysics,vol. 105, pp. 5467-5471,1996. T. Kamins, in Polycrystalline silicon for integrated circuits and displays, 2nd ed. Boston:Kluwer, 1988,pp. 296-310. I. Umezu,T. Kuwamura,K. Kitamura,andT. Tsuchida,"Effect of plasmatreatmenton the densityof defectsat an amorphousSi:H interface,"Journal of Applied Physics,vol. 84, pp. 1371-1377,1998. N. Ibaraki, K. Fukuda, and H. Takata, "The effect of interface-stateson amorphous silicon transistors,"IEEE Transactionson Electron Devices,'vol. 36, pp. 2971-2972, 1989.

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Chapter 6

SOLID PHASE CRYSTALLIZA TION: TECHNIQUES TO REALIZE SILICON-ONINSULATOR STRUCTURES

6.1 INTRODUCTION In chapter2 we discussedthe need for crystallization of precursoramorphous silicon (a-Si) films to obtain large grain polycrystalline silicon with smooth surfaces, and the various techniquesthat have been studied to realize it. One of the most prevalentand populartechniquesthat havegainedlot of interest,especiallyfor usein 3D ICs and displays,in the recent yearsis the solid phasecrystallizationof amorphous silicon films by furnaceannealing.Thereare severaladvantagesof this technique,like, low cost, simplicity, excellent uniformity, reproducibility, high throughputsby batch annealing, ease of large area-substrateprocessing, and higWy smooth surface morphologies1. In this chapterwe will discussin somedetail, the various techniques that have been reportedto achievesingle-crystallike Si on insulating substrates(SOl) by solid phasecrystallizationof precursora-Si films. However,the major drawbacksof the techniqueespeciallyfor usein fabrication

of silicon-on-insulator structures,are the long annealtime 2 typically requiredwhen glass substratesare employed, the fact that nucleation occurs randomly leading to

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Chapter6: Solid phasecrystallization:Techniquesto realizesilicon-on-insulatorstructures 163

random distribution of grain boundaries with random grain orientation in the silicon film, and the presence of crystalline defects within the grains of SPC polysilicon films. The detrimental effect of grain boundaries due to carrier trapping on the electrical

characteristicsof the polycrystalline silicon film is well documented3, 4. The grain boundary effect can be reduced by increasing the grain size of the polysilicon films and by controlling the location of the grain boundaries. Several techniques have been reported in the literature to increase the grain size of the a-Si films. As we discussedin chapter 2, the key is to increase the crystal growth rate and reduce the nucleation rate (equation 2.1). Due to the higher activation energy of nucleation compared to crystal growth 5, larger grains are most easily achieved by annealing at lower temperatures «650 °C) 2. Also, the nucleation rate is a strong function of the disorder in the precursor amorphous silicon films 6. Therefore, one obvious technique to increase grain size of polysilicon is to increase the disorder in the precursor a-Si films by either reducing the growth temperature (Section 3.34), or increasing the growth rate 6. Other techniques to increase the grain size involve a multiple-step anneal 7, suppressing nucleation at the a-Si/substrate interface through

incorporationof oxygen 8 or growth of double layers of a-Si 9 or using Si3N4coated glass substrates 1°, a high-temperature anneal after complete crystallization leading to

secondary grain growth 11, 12, and amorphization of polysilicon films by ion implantation such that a few small grains survive and during subsequentannealing these .)

crystalline regions grow to yield larger grains 5, 13. Section6.2 discussesthesegrainenhancementtechniques. Seeding selective regions of the a-Si film can control the location of grain boundaries. Subsequent lateral grain growth occurs in desired locations and transistors can be fabricated in these,selectiveregions within a particular grain with characteristics

Chapter6: Solid phasecrystallization:Techniquesto realizesilicon-on-insulatorstructures 164

close to that obtained for transistors in single-crystal Si. Various nucleation enhancement and seeding techniques have been studied for selective nucleation of a-Si films and also to reduce the crystallization time (as nucleation of seeds is usually the rate-limiting step during SPC of a-Si) as discussedin chapter 2. In our work we studied the hydrogen-plasma-seeding effect, as it might be the cleanest of all the nucleation enhancement methods, introducing the least amount of contamination and damage in the resulting polysilicon films. We also discussed the effect of controlled hydrogen plasma seeding in the source/drain regions of the transistor to realize higher field-effect mobility due to reduced number of grain boundaries in the channel in chapter 4. In this chapter (Section 6.3) we will discuss in further detail the various seeding techniques that have been tried to control the locations of grain boundaries and to achieve larger grains through the lateral-crystallization effect. In addition to controlling the location of grain boundaries and increasing the grain size, the defects within the grains should also be reduced (Section 6.4) and the grain orientation should be controlled (Section 6.5) to achieve ideally (I 00) vertical orientation, so as to realize single-crystal like behavior. In the following sections we will discuss these issues in some detail. 6.2 TECHNIQUES TO REALIZE LARGE GRAINS Direct deposition of silicon on insulating substrateslike SiO2 gives rise to either amorphous films or polycrystalline films with small grains (grain size < 100 nm) and rough surfaces, due to the amorphous nature of the insulating substrate (either glass or SiO2). As mentioned in the earlier section, solid phasecrystallization of amorphous Si is preferred method for obtaining SOl films. However, small grains and random grain boundaries can lead to scattering of the charge carriers and hence poor device properties. Various techniques have been tried to increase the grain size by reducing

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Chapter6: Solid phasecrystallization:Techniquesto realizesilicon-on-insulatorstructures 165

nucleation rates with respect to crystal growth rates. In the following sections we will discuss the several techniques that have been studied to achieve this. 6.2.1 Annealing temperature and effect of disorder in a-Si films Annealing temperature The final grain size of SPC annealedpolysilicon films depends on the annealing temperature, and the deposition temperature and the deposition rate of the precursor amorphous films. Calculation of relation between the average grain size and the growth and nucleation rates is a relatively complex problem. However, after many simplifying assumptions, the average grain size (g) can be written as 2 (for thin films) [~

g

= goe

3kT ]

(6.1)

where go is independent of temperature, En and Eg are the activation energy of nucleation and grain growth rate, respectively. From equation (6.1) we see that the grain size will increase with decreasing annealing temperature provided that En is greater than Eg. The value of En-Egis strongly dependent on the material properties of the precursor amorphous films with values of 0.25 eV for low pressure chemical vapor deposited (LPCV~) films and -2 eV for e-beam-evaporatedamorphous silicon 14,15. However, Koster 14has speculated that as the annealing temperature increases, at very high temperatures (>900 °C) the nucleation rate reduces while the crystal growth rate keeps increasing. The crystal growth rate reduces near the melting point temperature of silicon. This means that large grains can also be obtained by annealing at very high temperature where the nucleation rate starts to decreasewith temperature but a high growth rate can be maintained. Even under such conditions, the heating of the sample to that temperature range has to occur fast enough to avoid excessive nucleation during the temperature rise. r:

~c

Chapter6: Solid phasecrystallization:Techniquesto realizesilicon-on-insulatorstructures 166

Effect of disorder in a-Si films Large grains were also obtained for crystallization of a-Si films deposited at

lower temperatures6, 16,17and high growth rates 6. Increasing the structural disorder of the silicon network in the amorphous films resulted in reduced nucleation rates and thereby increased grain size for the crystallized films. The disorder of the underlying silicon network can be increased by utilizing low deposition temperatures combined with high deposition rates. Both parameters influence the surface diffusion length, which is a measure of the surface mobility of the silicon adatoms (adsorbed atoms) during deposition

18.

As the deposition temperature decreases or the deposition rate

increases the surface diffusion length reduces, resulting in the deposition of silicon films with higher structural disorder. The crystal growth rates were also found to be higher for more disordered structures, indicating a weaker bonding among the silicon atoms in the disordered structural matrix. The growth is probably enhanced due to the probability of atom rearrangement within a looser structure 6. Therefore a combination of suppressednucleation rate and enhancedcrystal growth (equation 2.1) ensures larger grains for films crystallized from disordered amorphous films. To illustrate this effect of disorder in the amorphous film on the final grain size of the crystallized films, consider the grain size of polysilicon obtained from crystallization of a-Si deposited by LPCVD using either silane or disilane. When silane is used in LPCVD the deposition rates are significantly reduced as the deposition temperature is reduced below 530 °c. Disilane, on the other hand, has been shown to result in the high deposition rates even at temperatures below 500 °c. Hence, films crystallized from a-Si obtained by the pyrolysis of disilane yielded larger grains 19. Low anneal temperature (under normal circumstances) and increased disorder in the amorphous silicon film are key to any technique involving grain size enhancement.

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Chapter6: Solid phasecrystallization:Techniquesto realizesilicon-on-insulatorstructures 167

6.2.2 Multiple-step anneal Large-grain polysi1icon was realized from multistep thermal annealing (MT A) utilizing the incubation time for nucleation due to the higher activation energy for nucleation 7. According to this method, crystallization takes place in steps, via heatingcooling cycles. In each cycle the wafer is annealed for a period which is less than the incubation time for nucleation and then cooled to a low temperature for relaxation. During each annealing period at high temperature, the seed grains grow to a certain extent, while spontaneousnucleation does not occur. The annealing process could then be designed so that the seed grains will grow by stepsuntil all the amorphous material is consumed, while nucleation is minimized or does not occur at all. A multistep thermal anneal process with a short high-temperature step to nucleate the film followed by a low-temperature step to maximize grain has also been reported 2°. This requires the ability to detect nucleation so that the temperature can be lowered. An acoustic sensorwas used to measurethe temperature of the wafer, from the

time of flight of acousticwavesthroughthe wafer 21. PZT transducersbondedto quartz !

pins are used to pulse ultrasonic Lamb waves through the sample. The measured delay exhibits a linear variation with temperature. The onset of nucleation was detected from the dip in temperature. The optical absorption coefficient of amorphous silicon film is reduced as it crystallizes. In rapid thermal annealing of films using tungsten halogen lamps (discussed previously in Section 2.2.2) using transparent substrates,this results in a reduction of heat absorption by the sample and therefore a reduction in substrate temperature. N-channel transistors made in such MTA films showed nearly 20 % increase in field-effect mobility with a corresponding increase of grain size compared to single-step-annealedfilms 2°.

Chapter6: Solid phasecrystallization:Techniquesto realizesilicon-on-insulatorstructures 168

6.2.3 Suppress nucleation at the a-Si/substrate interface As mentioned earlier, the key to increasing grain sizes of polysilicon films is to suppress nucleation rates so that the grain can grow larger without impinging on other grains. The interface of the precursor amorphous film/substrate (a-Si/SiOV is known to

provide large number of nucleation sites 6, 22. Several techniques have been tried to suppress this interface-nucleation involving either incorporation of oxygen at the

interface8 or growthof double-layers of a-Si films 9.We will discussthesetechniques in some detail next. Incorporation

of oxygen at the a-Si/SiO2 interface

It has been known that oxygen retards the crystallization process of a-Si during the solid phase epitaxial regrowth of oxygen-implanted a-Si

23.

Oxygen was therefore

incorporated at the a-Si/SiO2 interface during growth of the a-Si film by introducing oxygen into the LPCVD chamber before commencement of growth 8. This resulted in suppression of interface nucleation at the lower Si/SiO2 and nucleation occurred at other sites, namely the top surface. These films had fewer crystalline defects like microtwins and stacking faults, unlike the typical interface-nucleated films. These crystalline defects are typically

produced in interface-nucleated films to relieve the large

magnitude of tensile stress at the vicinity of the a-Si/SiO2 interface (also discussed in Section 3.3.5). The stress is formed by the phase transformation from amorphous to crystalline 24. For the case of the top-surface nucleation, the defects are not formed at the nucleation step since the stress is relieved at the surface 8. However, the stress gradually builds up at the growth front as the crystal grows, and when the stress increases above a critical level, defects are generated at the growth front. The surfacenucleated grains had equiaxial shape with {Ill

}-orientation and grain size of 3-5 ~m,

i

Chapter6: Solidphasecrystallization: Techniques to realizesilicon-on-insulator structures169

while conventionalSPCpolysilicon had elliptical grains with size of about 0.3-1~m 8. No dataon the electricalcharacteristicsof suchfilms was available. Double layer of a-Si film The other techniquereportedto suppressnucleationat the a-Si/SiO2interface involved deposition of double layers of amorphoussilicon deposited at different temperatures9. The bottom a-Si layer was depositedat lower temperature(higher disorder) to suppressthe nucleation, while the top layer was deposited at higher temperatureand hencenucleatewith smallernumberof nucleationsitesand maintainsa high growth rate.The depositiontemperatureof the top layer determinedthe incubation v

time for nucleationand the total crystallizationtime. This meansthat one can get the larger grains realized from annealingof low-temperaturedepositeda-Si films without paying penaltyof the longercrystallizationtime dueto slowernucleationrate.The grain size of the double layer film sequentiallydepositedat 150 °c and 200 °c enhancedto 1.8 ~m while that of the monolayerfilm depositedat 200 °c was 1.4 ~m. In fact the grain size improvedto 2.1 ~m when doublelayersdepositedsequentiallyat 65 and 200 °c, though at a penalty of longer crystallizationtime 9. Furtherstudy is requiredto find the limits of this processand determinethe effect of thicknessof the individual layers on the final grain size. 6.2.4 Secondarygrain growth Grain growth in polycrystalline silicon thin films proceeds through two fundamentallydifferent processes,namely normal grain growth and secondarygrain growth 11.When the initial grain size is smaller than the film thickness,normal grain growth leadsto a continuousincreasein the averagegrain size and the grain growth is three-dimensional.In this casethe averagegrain size increasesso that the total grain-

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